无符号连续运算除法器

1.起因：

       最近移植工程的时候要用到除法器，但是某国产FPGA的除法器IP核只支持单个数的除法，要等到这个除法运算结束后才能开始下一个数的除法运算，没办法做连续的除法运算。网上能找到的除法运算也是只支持单个数的除法运算，索性自己写一个

2.除法器原理

       见下面连接，写的比较详细清楚

       https://www.cnblogs.com/Dinging006/p/9382657.html.

3.FPGA代码

module divider
#(
  parameter  WIDTHN = 26,
             WIDTHD = 15
)
(
  numer,
  denom,
  clken,
  clk,
  reset,
  quotient,
  rfd
);

  input wire[WIDTHN-1:0]  numer;
  input wire[WIDTHD-1:0]  denom;
  input wire              clken;
  input wire              clk;
  input wire              reset;

  output wire[WIDTHN-1:0]  quotient;
  output wire              rfd; 

divider_b3c8e366d43b4ebbb7424ac7d85e03b7 
#(
  .WIDTHN   ( WIDTHN ),
  .WIDTHD   ( WIDTHD )
) 
divider_u (
  .numer    ( numer    ),
  .denom    ( denom    ),
  .clken    ( clken    ),
  .clk      ( clk      ),
  .reset    ( reset    ),
  .quotient ( quotient ),
  .rfd      ( rfd      )
);
  
endmodule



// *******************************
`resetall
`timescale 1ns / 1ps


module divider_b3c8e366d43b4ebbb7424ac7d85e03b7
#(
  parameter  WIDTHN = 26,
             WIDTHD = 15
)
(
  clk,
  reset,
  clken,
  numer,  
  denom,
  quotient, 
  rfd    
);
  
  input wire                clk;
  input wire                reset;
  //input start,
  input wire                clken;
  input wire[(WIDTHN-1):0]  numer;
  input wire[(WIDTHD-1):0]  denom;
  //output
  output reg[(WIDTHN-1):0]  quotient;
  output reg                rfd;
  
  reg [WIDTHN-1  :0]        clken_dly;
  reg [2*WIDTHN-1:0]        numer_tmp[WIDTHN:0];
  reg [2*WIDTHN-1:0]        denom_tmp[WIDTHN-1:0];
  
  wire[2*WIDTHN-1:0]        shift_numer[WIDTHN:1];
  reg [4:0]                 i;
  reg [4:0]                 j;

always@(posedge clk or posedge reset) 
  if(reset==1'd1) 
    clken_dly <= {WIDTHN{1'b0}};
  else 
    clken_dly <= {clken_dly[WIDTHN-2:0],clken};
        
always@(posedge clk or posedge reset) 
  if(reset==1'd1) 
  begin
    numer_tmp[0] <= {2*WIDTHN{1'b0}};
    denom_tmp[0] <= {2*WIDTHN{1'b0}};     
  end
  else if(clken==1'd1)
  begin
    numer_tmp[0] <= {{(WIDTHN-1){1'd0}},numer,1'b0};
    denom_tmp[0] <= {denom,{WIDTHN{1'd0}}};
  end

always@(posedge clk or posedge reset) 
  if(reset==1'd1) 
  begin
    for(j=1;j<WIDTHN;j=j+1)
    begin
      // numer_tmp[j] <= {2*WIDTHN{1'b0}};
      denom_tmp[j] <= {2*WIDTHN{1'b0}};   
    end
  end
  else 
  begin
    for(i=1;i<WIDTHN;i=i+1)
    begin
      denom_tmp[i] <= denom_tmp[i-1];
    end
  end

genvar k;
generate
    for(k=1;k<=WIDTHN;k=k+1)
    begin:loops
      assign shift_numer[k] = (numer_tmp[k-1]>denom_tmp[k-1])?(numer_tmp[k-1]-denom_tmp[k-1]+1'd1):numer_tmp[k-1];
      always@(posedge clk) 
        begin
          numer_tmp[k] <= {shift_numer[k][2*WIDTHN-2:0],1'b0};
        end       
    end
endgenerate

always@(posedge clk or posedge reset) 
  if(reset==1'd1) 
  begin
    rfd <= 1'd0;
    quotient <= {WIDTHN{1'b0}};
  end
  else 
  begin
    rfd <= clken_dly[WIDTHN-1];
    quotient <= shift_numer[WIDTHN][WIDTHN-1:0];
  end

    
endmodule

`timescale 1ns/1ns
module testbench();
     reg            sclk;
     reg            rst_n;
     reg            clken;
     
     initial
     begin
          sclk = 0;
          rst_n <= 0;
          #1010
          rst_n <= 1;
     end
     
     always#10 sclk = ~sclk;
     
    reg [25:0]      numer;
    reg [14:0]      denom;
    always@(posedge sclk or negedge rst_n) 
        if(rst_n==1'd0) 
        begin
          numer <= 26'd0;
          denom <= 15'd0;
          clken <= 1'd0;    
        end
        else
        begin
          numer <= {$random}%2048;
          denom <= {$random}%25;    
          clken <= {$random}%2;
        end


divider 
#(
  .WIDTHN   ( 26 ),
  .WIDTHD   ( 15 )
)
divider_init(
  .numer    (numer),
  .denom    (denom),
  .clken    (clken),
  .clk      (sclk),
  .reset    (~rst_n),
  .quotient (),
  .rfd      ()
);

endmodule

4.modelsim仿真结果