VHDL_ADC之cic_diffcell

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library edclib;
use edclib.pkg_xxxlib.all;　　-- package from company

 8 --! pipelined comb-chain for cic_filter
entity cic_diffcell is
generic
(
    Width        : natural := 20;        --! width        
    M           : natural := 1            --! difference fifo depth
); 
port
(
    RST         : in  std_logic;                            --! Async Reset
    C        : in  std_logic;                            --! Clock
    R         : in  std_logic;                            --! needed to clear  registers during sw-reset
    CEI         : in  std_logic;                            --! new data on input
    DIN        : in  std_logic_vector(Width-1 downto 0);    --! data in       
    CEO         : out std_logic;                            --! new data on output
    DOUT    : out std_logic_vector(Width-1 downto 0)    --! data out 
);
end cic_diffcell;

27 --! pipelined comb-chain for cic_filter
architecture asic of cic_diffcell is
type data_type is array (natural range <>) of std_logic_vector( Width-1 downto 0);    --! set of registers 
signal reg    : data_type(M downto 0);                        --! delay register (index 0 means DIN)
signal diff    : std_logic_vector( Width-1 downto 0);            --! subtraction

begin

reg(0) <= din when r='0' else (Width-2 => '1', others => '0');

37 --! stage delay
gdel: for i in 1 to M generate
    UDEL : REGDCE generic map(Width) port map(RST,C,CEI,reg(i-1),reg(i));
end generate;
     
42 --subtract
diff <= std_logic_vector( signed(din) - signed(reg(m)) ) when r='0' else (others => '0'); 

45 --Output-Reg (Sysclk delay)
UOREG: REGDCE generic map(Width) port map(RST,C,CEI, diff, DOUT);

48 --CE-chain
UCE: FFD port map(RST,C,CEI,CEO); 

end asic;