最近基于迅为的i.mx6Q开发板进行了一个FPGA项目的开发，下面给大家介绍一下EIM接口的配置，包括引脚的的选择和寄存器的配置
For the usage of WEIM on i.MX6, you don't need drivers for WEIM interface. But you must do some configurations for WEIM port like the following :
Let me assume you use 16bit Address lines and 16bit Data lines ,CS1 is for FPGA ChipSelect .
Address lines : EIM_DA0~EIM_DA15
Data lines : EIM_D16~EIM_D31
CS1 : Chip Select
(1)IOMUX configurations
All IOMUX settings for sabresd board are in board-mx6q_sabresd.c ,open it and add iomux for address lines ,data lines ,CS1 ,control lines to structure "static iomux_v3_cfg_t mx6q_sabresd_pads[] = {"
static iomux_v3_cfg_t mx6q_sabresd_pads[] = {
....
/*Address Lines*/
MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,
MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,
MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 ,
MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,
MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,
MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,
MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,
MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,
MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,
MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,
MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,
MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,
MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,
MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,
MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,
MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,
/*Data Lines*/
MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16,
MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17,
MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18,
MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19,
MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_22,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_23,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_24,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_25,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_26,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_27,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_28,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_29,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_30,
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_31,
/*Control Lines*/
MX6Q_PAD_EIM_RW__WEIM_WEIM_RW,// write signal
MX6Q_PAD_EIM_OE__WEIM_WEIM_OE,// read signal
//perhaps following 2 signals are not used.
MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT,// shakehand signal used to sync mode.
MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK,// Burst clock used to burst and sync mode.
MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA,// used to burst mode
/*Chip select line*/
MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1,
....
}
(2)Distributing Memory Space For WEIM_CS1
By Defaul,The total 128MB space are all for EIM_CS0,so We should reconfigure space.
In Register IOMUXC_GPR1 ,Bit[5:4] determines address spcace on EIM_CS1
Let us set it 64MB:
bit[5:4] = 01
bit[3]= 1 // Make WEIM_CSI to be Active.
(3)Configuring IOMUX mode
We use 16 bit non-mux mode, So we should configure Register On EIM_CS1. See "Table 22-1. EIM multiplexing" : 16bit,MUM=0,DSZ=010
You should configure EIM_CS1GCR1 register according to the mode that you want. More details , See imx61qrm.pdf , page 1038.
(4)Read/Write Setting
Read: EIM_CSnRCR1/EIM_CSnRCR2
Write: EIM_CSnWCR1/EIM_CSnWCR2