阶段二计数器练习13

module cnt_test(
                clk,
                rst_n,
                en1,
//                en2,
//                en3,
                dout
);

input     clk;
input     rst_n;
input      en1;
//input      en2;
//input      en3;

output [2:0] dout;

reg [2:0]    dout;
reg         flag_add;

reg [3:0] cnt0;
reg [3:0] cnt1;
reg [3:0] x;
reg [3:0] y;
//reg [3:0] z;
//reg [3:0] flag_sel;
 
wire add_cnt0;
wire end_cnt0;

wire add_cnt1;
wire end_cnt1;

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt0 <= 0;
    end
    else if(add_cnt0)begin
        if(end_cnt0)begin
            cnt0 <= 0;
        end
        else begin
            cnt0 <= cnt0 + 1;
        end
    end
end

assign add_cnt0 = flag_add;
assign end_cnt0 = add_cnt0 && cnt0 == x - 1; 

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt1 <= 0;
    end
    else if(add_cnt1)begin
        if(end_cnt1)begin
            cnt1 <= 0;
        end
        else begin
            cnt1 <= cnt1 + 1;
        end
    end
end

assign add_cnt1 = end_cnt0;
assign end_cnt1 = add_cnt1 && cnt1 == 3 - 1; 

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        flag_add <= 0;
    end
    else if(en1)begin
        flag_add <= 1;
    end
    else if(end_cnt1)begin
        flag_add <= 0;
    end
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        dout <= 0;
    end
    else if(add_cnt0 && cnt0 == 1-1)begin
        dout <= y;
    end
    else if(end_cnt0)begin
        dout <= 0;
    end
end

always @(*)begin
    if(cnt1 == 0)begin
        x = 4;
        y = 3;
    end
    else if(cnt1 == 1)begin
        x = 3;
        y = 2;
    end
    else begin //省去if(cnt1 == 2) 
        x = 2;
        y = 1;
    end
end

endmodule