TimingTool - The Timing Diagram
TimingTool is designed to give electronics engineers an easy to use graphical interface for entering
and editing timing diagrams commonly seen in digital electronic design.
TimingTool is intuitive in use and always presents the most useful properties of selected objects for easy access
Diagrams for analysis, design and documentation may be created quickly and efficiently,
benefiting workflow saving time and money.
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Diagrams for Documentation – Diagrams may be exported in a variety of formats for documentation.
All common graphics and word processing packages are supported with bitmap, scalable vector and pdf formats. -
Timing Analysis – The parameter driven timing analysis engine automatically calculates delay paths,
set-up and hold violations, measures and guarantees. Complex timing problems may be quickly identified and corrected. -
Automated HDL test bench Generation – TimingTool has the capability of translating a timing diagram into HDL (VHDL or Verilog)
to aid productivity when producing test benches and other forms of timing related HDL code. -
Timing Diagrams on the Web – Data sheets may be exported directly to HTML for instant publication to the web/intranet.
Timing diagrams can be uploaded to on-line work areas.
These may be accessed globally with TimingTool-Lite the free-to-use on-line timing diagram editor,
enabling development teams to share information between sites and offices. -
Adaptable – A powerful macro scripting language permits TimingTool Editor to perform custom tasks.
Use macros to perform specialised exports or imports. -
Si2 TDML Standard – TimingTool documents are completely TDML compliant.
TDML is anXML based standard for recording timing diagram information,
which has been developed by the Si2 organisation.