verilog 计算机网络 仿真 激励 pcap

做verilog网络逻辑时，需要产生正确的数据包格式激励，手写激励真烦人，现在让testbench读取pcap文件，则可以精确还原数据包的bit与时序，省去了一大批麻烦

1.设计读取逻辑

`timescale 1ns / 1ps
`define NULL 0

// Coder:    joe
// Description:
//    将pcap文件中的数据包读出来，8bit位宽
//  
//   
//
//  
//

module PcapParser
    #(
        parameter pcap_filename = "none",
        parameter ipg = 32
    ) (
        input CLOCK,
        input pause,
        output reg available = 0,
        output reg datavalid = 0,
        output reg [7:0] data = 0,
        output reg [7:0] pktcount = 0,
        output reg newpkt = 0,
        output reg pcapfinished = 0
    );
        
    

    // buffers for message
    reg [7:0] global_header [0:23];
    reg [7:0] packet_header [0:15];

    integer swapped = 0;
    integer toNanos = 0;
    integer file = 0;
    integer r    = 0;
    integer eof  = 0;
    integer i    = 0;
    integer pktSz  = 0;
    integer diskSz = 0;
    integer countIPG = 0;

    initial begin
        

        // open pcap file
        if (pcap_filename == "none") begin
            $display("pcap filename parameter not set");
            $finish_and_return(1);
        end

        file = $fopen(pcap_filename, "rb");
        if (file == `NULL) begin
            $display("can't read pcap input");
            $finish_and_return(1);
        end

        // read binary global_header
        // r = $fread(file, global_header);
        r = $fread(global_header,file);

        // check magic signature to determine byte ordering
        if (global_header[0] == 8'hD4 && global_header[1] == 8'hC3 && global_header[2] == 8'hB2) begin
            $display(" pcap endian: swapped, ms");
            swapped = 1;
            toNanos = 32'd1000000;
        end else if (global_header[0] == 8'hA1 && global_header[1] == 8'hB2 && global_header[2] == 8'hC3) begin
            $display(" pcap endian: native, ms");
            swapped = 0;
            toNanos = 32'd1000000;
        end else if (global_header[0] == 8'h4D && global_header[1] == 8'h3C && global_header[2] == 8'hb2) begin
            $display(" pcap endian: swapped, nanos");
            swapped = 1;
            toNanos = 32'd1;
        end else if (global_header[0] == 8'hA1 && global_header[1] == 8'hB2 && global_header[2] == 8'h3c) begin
            $display(" pcap endian: native, nanos");
            swapped = 0;
            toNanos = 32'd1;
        end else begin
            $display(" pcap endian: unrecognised format %02x%02x%02x%02x", global_header[0], global_header[1], global_header[2], global_header[3] );
            $finish_and_return(1);
        end
    end

    always @(posedge CLOCK)
    begin
        if (eof == 0 && diskSz == 0 && countIPG == 0) begin
            // read packet header
            // fields of interest are U32 so bear in mind the byte ordering when assembling
            // multibyte fields
            r = $fread(packet_header, file);
            eof = $feof(file);

            if ( eof == 0) begin
                if (swapped == 1) begin
                    pktSz  = {packet_header[11],packet_header[10],packet_header[9] ,packet_header[8] };
                    diskSz = {packet_header[15],packet_header[14],packet_header[13],packet_header[12]};
                end else begin
                    pktSz =  {packet_header[ 8],packet_header[ 9],packet_header[10],packet_header[11]};
                    diskSz = {packet_header[12],packet_header[13],packet_header[14],packet_header[15]};
                end

                $display("  packet %0d: incl_length %0d orig_length %0d eof %0d", pktcount, pktSz, diskSz, eof );

                available <= 1;
                newpkt <= 1;
                pktcount <= pktcount + 1;
                countIPG <= ipg;    // reload interpacket gap counter
            end
        end else if ( diskSz > 0) begin

            // packet content is byte-aligned, no swapping required
            if (~pause) begin
                newpkt <= 0;
                diskSz <= diskSz - 1;
                data <= $fgetc(file);
                eof = $feof(file);
                if ( eof != 0 || diskSz == 1) begin
                    available <= 0;
                end else begin
                    datavalid <= 1;
                end
            end else begin
                datavalid <= 0;
            end
        end else if (countIPG > 0) begin
            countIPG <= countIPG - 1;
        end else if (eof != 0) begin
            pcapfinished <= 1;    // terminal loop here
        end


    end

endmodule

2.编写testbench文件

将 tcp-4846-connect-disconnect.pcap 文件放在工程目录下。自己随意放置一个，然后修改源码中文件的名称，才可以读到。

`timescale 1ns / 1ps
`define NULL 0

// Coder:    joe
// Description:
//    测试文件，读取数据，打入模块
//  
//   
//
//  
//

module PcapParser_test
#(
        parameter DATA_WIDTH = 480,
        parameter CTRL_WIDTH=32,
        parameter STAGE_NUMBER = 2,
        parameter NUM_QUEUES = 8
    );

    // Inputs
    reg CLOCK = 0;
    reg paused = 0;
    reg rst=0;
    wire available;
    wire [7:0] pktcount;
    wire streamvalid;
    wire [7:0] stream;
    wire pcapfinished;
    wire newpkt;
    
    wire out_wr;
    wire [CTRL_WIDTH-1:0] out_ctl;
    wire [DATA_WIDTH-1:0] out_data;
    
    wire out_wr1;
    wire [CTRL_WIDTH-1:0] out_ctl1;
    wire [DATA_WIDTH-1:0] out_data1;

    // Instantiate the Unit Under Test (UUT)
    PcapParser #(
        .pcap_filename( "tcp-4846-connect-disconnect.pcap" )
    ) pcap (
        .CLOCK(CLOCK),
        .pause(paused),
        .available(available),
        .datavalid(streamvalid),
        .data(stream),
        .pktcount(pktcount),
        .newpkt(newpkt),
        .pcapfinished(pcapfinished)
    );
    

    always #10 CLOCK = ~CLOCK;
    
    //always #100 paused = ~paused;

    integer i;

    initial begin

        $dumpfile("pcap.lxt");
        //$dumpvars(0);

        // Initialize Inputs
        $display("Reading from pcap");

        // Wait 100 ns for global reset to finish
        #10; 
        rst = 1;

        // Add stimulus here
        while (~pcapfinished ) begin
            //$display("stream: %8d %x %d %x %x %c", i, paused, pktcount, streamvalid, stream, stream);
            #20
            i = i+1;
        end

        $finish;

    end

endmodule

3.读取仿真激励结果

=====================

qsy

2018-7-5 11:39:44