module state(CLOCK,RESET,LED,KEY_UP);
input CLOCK,RESET,KEY_UP;
output reg [3:0] LED;
parameter s1=2'b00,s2=2'b01,s3=2'b10,s4=2'b11;
reg [1:0] current_state,next_state;
reg t;
parameter T1s=23'd2_000_00000;
reg [22:0] cnt;
always @ (posedge CLOCK or negedge RESET)
if(!RESET)
begin
cnt<=0;
t<=0;
end
else if(cnt==T1s)
begin
cnt<=0;
t<=~t;
end
else
cnt<=cnt+1;
//assign t=(cnt==T1s)? 1'b1:1'b0;
always @ (posedge t or negedge RESET)
if(!RESET)
current_state<=s1;
else
current_state<=next_state;
always @ (current_state)
begin
next_state=s1;
case(current_state)
s1: if(KEY_UP) next_state=s2;else next_state=s4;
s2: if(KEY_UP) next_state=s3;else next_state=s1;
s3: if(KEY_UP) next_state=s4;else next_state=s2;
s4: if(KEY_UP) next_state=s1;else next_state=s3;
default: next_state=s1;
endcase
end
always @ (posedge t or negedge RESET)
if(!RESET)
LED<=4'b0000;
else
case(next_state)
s1: LED<=4'b0001;
s2: LED<=4'b0010;
s3: LED<=4'b0100;
s4: LED<=4'b1000;
default: LED<=4'bzzzz;
endcase
endmodule