一、CRC的实现方法
对于一个比特串，假如要生成 n-bit 的CRC，那么CRC的多项式用(n+1)位表示。生成CRC的步骤如下：
1、比特串后面附加n个0；
2、(n+1)与比特串最左对齐，做异或；
3、(n+1)逐比特右移，并异或；
4、直至原比特串全部为0，剩下的n比特即为CRC。
校验CRC的方法是：
1、CRC附于收到的比特串后面；
2、(n+1)异或、移位；
3、最后结果，如果包含附加CRC之后的比特串为0，证明传输无误。
二、硬件实现CRC的建议
由于异或门天生的缺陷，在硬件实现CRC时，会出现一些与常用处理方法相反的的建议。
… XOR gates have a cancellation property that creates exceptionally large number of reasonable factoring combinations, so synthesis tools cannot always choose the best result by default.
Altera的建议如下：
1、If performance is important, optimize for speed
Quartus II 默认的优化方式是 area optimization
2、Use separate CRC blocks instead of cascaded stages
It is typically better to create full separate CRC blocks for each data width that you require in the design, and then multiplex them together to choose the appropriate mode at a given time.
3、Use separate CRC blocks instead of allowing blocks to merge
… the CRC logic allows significant reductions, but this works best when each CRC function is optimized separately.
… If you are having problems with the quality of results and you see that two CRC functions are sharing logic, ensure that the blocks are synthesized independently using one of the following methods:
2和3的整体意思是，不要用小模块，不要复用功能块。
4、Take advantage of latency if available
… insert an extra bank of registers at the input and allow the retiming feature to move the registers for better results( using Perform gate-level register retiming ). You can also build the CRC unit half as width and alternate between halves of the data in each clock cycle.
5、Save power by disabling CRC blocks when not in use
… To save power, use clock enables to disable the CRC function for every clock cycle that the logic is not required.
… It is valuable to disable the CRC function even for this short amount of time.
