按时间周期性产生脉冲:
module maichong ( output q1,q2,q3,
input clk, input d, input rst ); reg q; always @ (posedge clk or negedge clk) begin if(!rst) q<=0; else d[2:1]<=d[1:0];
d[0]<=d[2];
q1<=d[2];
q2<=d[1];
q3<=d[0]; end
按时间周期性产生脉冲:
module maichong ( output q1,q2,q3,
input clk, input d, input rst ); reg q; always @ (posedge clk or negedge clk) begin if(!rst) q<=0; else d[2:1]<=d[1:0];
d[0]<=d[2];
q1<=d[2];
q2<=d[1];
q3<=d[0]; end