1. 38译码器

38译码器

---

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_signed.all;


entity top is
port (
        sel: in std_logic_vector (2 downto 0);
        y: out std_logic_vector(7 downto 0)
--    sel : in bit;
--    y : out bit
    
);
end top;

architecture Behavioral of top is

begin
process (sel)

begin
--if(sel='0') then y<='0';
--else y<='1';
--end if;
    case sel is
        when "000" => y<="00000001";
        when "001" => y<="00000010";
        when "010" => y<="00000100";
        when "011"  => y<="00001000";
        when "100"=> y<="00011000";
        when "101" => y<="00100000";
        
        when "110" => y<="01000000";
        when "111" => y<="10000000";
        when others =>null;
    end case;
end process;
end Behavioral;