CVO实现过程

   



 module vid_cvo #(
        parameter H_SYNC                 =  44,
        parameter H_FRONT_PORCH =  88,
        parameter H_BACK_PORCH  = 148,
        parameter V_SYNC            =   5,
        parameter V_FRONT_PORCH =   4,
        parameter V_BACK_PORCH  =  36
    
    
    )(
        input             clk,
        input             rst_p,
        input     [15:0] idata,
        input             ivalid,
        input             vid_sop,
        input             vid_eop,
        
//        input [5:0] h_sync_pixcels,
//        input [5:0] h_front_porch_pixcels,
//        input [5:0] h_back_porch_pixcels,
//        input [5:0] v_sync_lines,
//        input [5:0] v_front_porch_lines,
//        input [5:0] v_back_porch_lines,
        
        output reg din_ready,
        
        input [12:0] col,
        input [12:0] row,
        
        output reg[15:0] odata,
        output reg v_sync,
        output reg h_sync,
        output reg de
        
        
        
    );
    
    
    parameter S_H_SYNC = 2'b00;
    parameter S_H_BACK_PORCH = 2'b01;
    parameter S_H_ACTIVE   = 2'b10;
    parameter S_H_FRONT_PORCH = 2'b11;
    parameter S_V_SYNC = 2'b00;
    parameter S_V_BACK_PORCH = 2'b01;
    parameter S_V_ACTIVE   = 2'b10;
    parameter S_V_FRONT_PORCH = 2'b11;
    
    
    
    reg [1:0] h_pre_state = S_H_SYNC;
    reg [1:0] h_nx_state = S_H_SYNC;
    reg [1:0] v_pre_state = S_V_SYNC;
    reg [1:0] v_nx_state = S_V_SYNC;
    
    reg [12:0] h_cnt     = 0;
    reg [12:0] v_cnt     = 0;
    reg [15:0] sync_code = 0;
    reg           de_r     = 1'b0;
//    reg [15:0] data_r1 = 16'd0;
//    reg [15:0] data_r2 = 16'd0;
//    reg [15:0] data_r3 = 16'd0;
//    reg [15:0] data_r4 = 16'd0;
    wire             fifo_wr_en ;
    wire [15:0] fifo_wr_data;
    wire             fifo_almost_full;
    wire            fifo_almost_empty;
    wire [15:0] fifo_rd_data;
    reg            fifo_rd_en = 1'b0;
    reg             vid_sop_r = 1'b0;
    wire            pos_vid_sop;
    reg                fifo_rst_p = 1'b1;
    reg                fifo_rd_valid = 1'b0;
    reg [15:0] fifo_rd_data_r = 16'd0;
    reg [15:0] sync_code_r = 16'd0;
    reg [15:0] sync_code_r1 = 16'd0;
    reg                  de_r1 = 1'b0;
    reg                    de_r2 = 1'b0;
    reg                    h_sync_r = 1'b0;
    reg                    h_sync_r1 = 1'b0;
    reg                    h_sync_r2 = 1'b0;
    reg                    v_sync_r  = 1'b0;
    reg                    v_sync_r1 = 1'b0;
    reg                    v_sync_r2 = 1'b0;
        

    
    
    always @( posedge clk )
    begin
        vid_sop_r <= vid_sop;
    end
    
    assign pos_vid_sop = {vid_sop_r,vid_sop} == 2'b01;
    
    
    
    
    assign fifo_wr_en = (vid_sop | vid_eop ) ?1'b0: ivalid ?1'b1 :1'b0; 
    assign fifo_wr_data = idata;
    
    always @( posedge clk )
    begin
        if( fifo_almost_empty )
                 din_ready<= 1'b1;
        else if( fifo_almost_full )
                din_ready <= 1'b0;
        else
                din_ready <= 1'b0;
    end
    
    always @( posedge clk )
    begin
            if( rst_p )
                    fifo_rst_p <= 1'b1;
            else if( pos_vid_sop )
                    fifo_rst_p <= 1'b0;
            else
                    fifo_rst_p <= fifo_rst_p;
    end
    
    
    
    fifo_w18d512    fifo_w18d512_inst (
    .clock ( clk ),
    .data ( fifo_wr_data ),
    .rdreq ( fifo_rd_en ),
    .sclr ( fifo_rst_p ),
    .wrreq ( fifo_wr_en ),
    .almost_full ( fifo_almost_full ),
    .almost_empty( fifo_almost_empty),
    .empty (  ),
    .full (  ),
    .q ( fifo_rd_data ),
    .usedw (  )
    );
    always @( posedge clk )
    begin
            if( h_nx_state == S_H_ACTIVE && v_nx_state == S_V_ACTIVE )
                    fifo_rd_en <= 1'b1;
            else
                    fifo_rd_en <= 1'b0;
    end
    
    always @( posedge clk )
    begin
            fifo_rd_valid <= fifo_rd_en;
    end
    
    always @( posedge clk )
    begin
            if( fifo_rd_valid )
                    fifo_rd_data_r <= fifo_rd_data;
            else
                    fifo_rd_data_r <= 16'd0;
    end
    
/***********************************************************************

***********************************************************************/    
    
    always @( posedge clk )//or posedge rst_p
    begin
            if( fifo_rst_p ) begin 
                h_pre_state <= S_H_SYNC;
                v_pre_state <= S_V_SYNC;

            end else begin 
                h_pre_state <= h_nx_state;
                v_pre_state <= v_nx_state;
            end 
    end
    
    always @( * )
    begin
            case( h_pre_state )
            S_H_SYNC :
                    if( h_cnt == H_SYNC -1 )
                            h_nx_state  <= S_H_BACK_PORCH;
                    else
                            h_nx_state <= S_H_SYNC;
            
            S_H_BACK_PORCH :
            begin
                    if( h_cnt == H_BACK_PORCH -1 )        
                            h_nx_state  <= S_H_ACTIVE;
                    else                            
                            h_nx_state <= S_H_BACK_PORCH;       
            end
            S_H_ACTIVE    :
            begin
                   if( h_cnt == col -1 )     
                        h_nx_state  <= S_H_FRONT_PORCH;           
                else                                   
                        h_nx_state <= S_H_ACTIVE;        
                    
            end
            S_H_FRONT_PORCH :    
            begin
                if( h_cnt == H_FRONT_PORCH -1 )                
                        h_nx_state  <= S_H_SYNC;    
                else                                 
                        h_nx_state <= S_H_FRONT_PORCH;          
                  
            end        
            default:;
            endcase    
                            
    end
    
    always @( * )
    begin
            case( v_pre_state )
            S_V_SYNC :
            begin 
                    if( h_nx_state == S_H_SYNC &&  h_pre_state  == S_H_FRONT_PORCH  ) begin
                            if( v_cnt == V_SYNC -1 )
                                    v_nx_state = S_V_BACK_PORCH;
                            else
                                v_nx_state = S_V_SYNC;
                    end else begin
                            v_nx_state = S_V_SYNC;
                    end
            end
            S_V_BACK_PORCH :
            begin
                    if( h_nx_state == S_H_SYNC &&  h_pre_state  == S_H_FRONT_PORCH  ) begin
                            if( v_cnt == V_BACK_PORCH -1 )        
                                    v_nx_state = S_V_ACTIVE;
                            else
                                    v_nx_state = S_V_BACK_PORCH;    
                    end else begin
                            v_nx_state = S_V_BACK_PORCH;  
                    end  
            end
            S_V_ACTIVE    :
            begin
                    if( h_nx_state == S_H_SYNC &&  h_pre_state  == S_H_FRONT_PORCH  ) begin
                           if( v_cnt == row -1 )     
                                v_nx_state = S_V_FRONT_PORCH;
                            else
                                    v_nx_state = S_V_ACTIVE; 
                end else begin
                        v_nx_state = S_V_ACTIVE; 
                end       
                    
            end
            S_V_FRONT_PORCH :    
            begin
                    if( h_nx_state == S_H_SYNC &&  h_pre_state  == S_H_FRONT_PORCH  ) begin
                        if( v_cnt == V_FRONT_PORCH -1'b1 )                
                                v_nx_state = S_V_SYNC;
                            else
                                    v_nx_state = S_V_FRONT_PORCH; 
                    end else begin
                            v_nx_state = S_V_FRONT_PORCH;
                    end
            end        
            default:;
            endcase    
//            end else begin
//                    v_nx_state = v_nx_state;
//            end
//    
    end
/***********************************************************************
cnt
***********************************************************************/
    always @( posedge clk )
    begin
        if( fifo_rst_p ) begin
            h_cnt <= 0;
        end else begin 
            case( h_nx_state )
            S_H_SYNC :
            begin 
                     if( h_pre_state == S_H_FRONT_PORCH  )  //&& h_cnt == H_FRONT_PORCH -1
                            h_cnt <= 0;
                    else
                            h_cnt <= h_cnt + 1'b1;
            end 
            S_H_BACK_PORCH :
            begin
                    if( h_pre_state == S_H_SYNC )//&& h_cnt == H_SYNC -1)
                            h_cnt <= 0;
                    else                            
                            h_cnt <= h_cnt + 1'b1;       
            end
            S_H_ACTIVE    :
            begin
                if( h_pre_state == S_H_BACK_PORCH)// && h_cnt == H_BACK_PORCH -1)
                        h_cnt <= 0;           
                else                                   
                        h_cnt <= h_cnt + 1'b1;        
            end
            S_H_FRONT_PORCH :    
            begin
                if( h_pre_state == S_H_ACTIVE )//&& h_cnt == col -1)
                        h_cnt <= 0;   
                else                                 
                        h_cnt <= h_cnt + 1'b1;       
            end        
            default:;
            endcase    
    end
    end 
    
    always @( posedge clk or posedge fifo_rst_p )
    begin
        if( fifo_rst_p)
            v_cnt <= 0;
        else  begin 
            if( h_nx_state == S_H_SYNC &&  h_pre_state  == S_H_FRONT_PORCH  ) 
            begin
                case( v_nx_state )
                S_V_SYNC :
                begin
                    if( v_pre_state == S_V_FRONT_PORCH )
                            v_cnt <= 0;
                    else
                            v_cnt <= v_cnt + 1'b1;
                end
            
                S_V_BACK_PORCH :
                begin
                    if( v_pre_state  ==  S_V_SYNC )        
                            v_cnt <= 0;
                    else                            
                            v_cnt <= v_cnt + 1'b1;       
                end
                S_V_ACTIVE    :
                begin
                   if( v_pre_state  ==  S_V_BACK_PORCH )     
                        v_cnt <= 0;           
                else                                   
                        v_cnt <= v_cnt + 1'b1;        
                    
                end
                S_V_FRONT_PORCH :    
                begin
                if( v_pre_state  ==  S_V_ACTIVE )               
                        v_cnt <= 0;   
                else                                 
                        v_cnt <= v_cnt + 1'b1;       
                  
                end        
                default:;
                endcase    
            end
        end
    end
    
/***********************************************************************
h_sync v_sync de 
***********************************************************************/    
    always @( posedge clk )
    begin
            if( h_nx_state == S_H_SYNC )
                    h_sync_r <= 1'b1;
            else
                    h_sync_r <= 1'b0;
    end
    
    always @( posedge clk )
    begin
            if( v_nx_state == S_V_SYNC )
                    v_sync_r <= 1'b1;
            else
                    v_sync_r <= 1'b0;
    end
    
    always @( posedge clk )
    begin
            if( h_nx_state == S_H_ACTIVE && v_nx_state == S_V_ACTIVE )
                    de_r <= 1'b1;
            else
                    de_r <= 1'b0;
    end
/***********************************************************************

***********************************************************************/    
    
    always @( posedge clk )
    begin
        if(( h_nx_state == S_H_BACK_PORCH) && ( v_nx_state == S_V_SYNC || v_nx_state == S_V_BACK_PORCH || v_nx_state == S_V_FRONT_PORCH))
                case( h_cnt )
                        H_BACK_PORCH -2 : sync_code <= 16'habab;
                        H_BACK_PORCH -3 : sync_code <= 16'h0000;
                        H_BACK_PORCH -4 : sync_code <= 16'h0000;
                        H_BACK_PORCH -5 : sync_code <= 16'hffff;
                default:sync_code <= 16'd0;
                endcase
        else if(( h_nx_state == S_H_FRONT_PORCH) && ( v_nx_state == S_V_SYNC || v_nx_state == S_V_BACK_PORCH || v_nx_state == S_V_FRONT_PORCH))
                if( h_pre_state == S_H_ACTIVE)
                        sync_code <= 16'hffff;
                else begin
                    case(h_cnt )        
                        0 : sync_code <= 16'h0000;
                        1 : sync_code <= 16'h0000;
                        2 : sync_code <= 16'hb6b6;      
                    default:sync_code <= 16'd0;
                    endcase
                end
        else if(( h_nx_state == S_H_BACK_PORCH) && ( v_nx_state == S_V_ACTIVE)) begin   
            case(h_cnt )                       
                      H_BACK_PORCH -2 : sync_code <= 16'h8080;      
                      H_BACK_PORCH -3 : sync_code <= 16'h0000;      
                      H_BACK_PORCH -4 : sync_code <= 16'h0000;      
                      H_BACK_PORCH -5 : sync_code <= 16'hffff;         
              default:sync_code <= 16'd0;                      
              endcase                        
        end
        else if(( h_nx_state == S_H_FRONT_PORCH) && ( v_nx_state == S_V_ACTIVE)) begin
                if( h_pre_state == S_H_ACTIVE)
                        sync_code <= 16'hffff;
                else begin
                    case(h_cnt )                       
                            0 : sync_code <= 16'h0000;      
                            1 : sync_code <= 16'h0000;      
                            2 : sync_code <= 16'h9d9d;         
                    default:sync_code <= 16'd0;                      
                    endcase  
                end                       
        end
        else begin
                    sync_code <= 16'd0;
        end
    end
/***********************************************************************
sync
***********************************************************************/    
    
    always @( posedge clk )
    begin
        sync_code_r <= sync_code;
        sync_code_r1<= sync_code_r;
        de_r1 <= de_r;
        de_r2 <= de_r1;
        h_sync_r1 <= h_sync_r;
        h_sync_r2 <= h_sync_r1;
        v_sync_r1 <= v_sync_r;
        v_sync_r2 <= v_sync_r1;
        
    end
    always @( posedge clk )
    begin
            odata <= sync_code_r1 + fifo_rd_data_r;
            h_sync <= h_sync_r2;
            v_sync <= v_sync_r2;
            de     <= de_r2;
    end
    

    
    endmodule