希望大家看看，给指点一下，程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ZL_multiplier is
port(
clk : in std_logic;
reset : in std_logic;
mul1 : in std_logic_vector(3 downto 0);
mul2 : in std_logic_vector(3 downto 0);
product : out std_logic_vector(7 downto 0)
);
end ZL_multiplier;
architecture behaver of ZL_multiplier is
component full_adder
port(
add1 : in std_logic;
add2 : in std_logic;
fc : in std_logic;
sum : out std_logic;
co : out std_logic
);
end component;
component half_adder
port(
add1 : in std_logic;
add2 : in std_logic;
sum : out std_logic;
co : out std_logic
);
end component;
signal a, x : std_logic_vector (3 downto 0);
signal p : std_logic_vector (7 downto 0);
signal m : std_logic_vector(11 downto 0);
signal c : std_logic_vector(11 downto 0);
begin
x <= mul1;
a <= mul2;
product <= p;
p(0) <= x(0) and a(0);
h0 : half_adder
port map(a(0) and x(1),a(1) and x(0),m(0),c(0));
p(1) <= m(0);
h1 : half_adder
port map(a(1) and x(1),a(2) and x(0),m(1),c(1));
f0 : full_adder
port map(a(0) and x(2),m(1),c(0),m(2),c(2));
p(2) <= m(2);
f1 : full_adder
port map(a(2) and x(1),a(3) and x(0),c(1),m(3),c(3));
f2 : full_adder
port map(a(0) and x(3),a(1) and x(2),c(2),m(4),c(4));
h2 : half_adder
port map(m(3),m(4),m(5),c(5));
p(3) <= m(5);
f3 : full_adder
port map(a(2) and x(2),a(3) and x(1),c(3),m(6),c(6));
f4 : full_adder
port map(a(1) and x(3),m(6),c(4),m(7),c(7));
h3 : half_adder
port map(m(7),c(5),m(8),c(8));
p(4) <= m(8);
f5 : full_adder
port map(a(2) and x(3),a(3) and x(2),c(6),m(9),c(9));
f6 : full_adder
port map(c(7),c(8),m(9),m(10),c(10));
p(5) <= m(10);
f7 : full_adder
port map(a(3) and x(3),c(9),c(10),m(11),c(11));
p(6) <= m(11);
p(7) <= c(11);
end behaver;