pyhcl语法

大致格式

• <<= is a connect operator, 说明之间有线连着，类似chisel里的:=
• 例子：

class ALU(Module):
    io = IO(
        a=Input(U.w(32)),
        b=Input(U.w(32)),
        ctl=Input(U.w(2)),
        out=Output(U.w(32)),
    )

    io.out <<= LookUpTable(io.ctl, {
        ALU_Op.ALU_ADD: io.a + io.b,
        ALU_Op.ALU_SUB: io.a - io.b,
        ALU_Op.ALU_MUL: io.a * io.b,
        ALU_Op.ALU_DIV: io.a / io.b,
        ...: U(0)
    })

生成firrtl文件和verilog文件

• call function compile_to_firrtl(Adder, "Adder.fir")
• call firrtl compiler firrtl -i Adder.fir
• 或者直接在python文件里面写

Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Adder()), "Adder.fir"))

数据类型

• unsigned integer :U
• signed integer : S
• boolean: Bool
• 例子

U(1)	# 1-bit unsigend decimal value 1
U(0x126) # 12-bit unsigned hexadecimal value 0x126
U.w(4)(10) # 4-bit unsigned decimal value 10
S.w(16)(0x11) # 16-bit signed hexadecimal value 0x11
Bool(True)	# Boolean literal values True

• U.w(<width>)(<values>)
• Reg, Wire, and I/O ports.

s = Reg(U.w(16))	# 16-bit unsigned integer register
alt = Wire(S.w(32))	# 32-bit signed integer wire
cout = Output(Bool)	# Boolean output port

• vector

# Vec(<size>, <cdatatype>)
rarray = Reg(Vec(4, U.w(16)))	# A 16-bit 4 length unsigned integer register array
# rarray = [U(0), U(1), U(2), U(3)]
for i in range(0, 4):
  rarray[i] <<= U(i)
a=Input(Vec(4, U.w(16)))

• Bundle

breg = Reg(Bundle(
  x=U.w(16),
  y=S.w(16),
  z=Bool
))

breg.x <<= U(12)
breg.y <<= S(4)
breg.z <<= Bool(False)
io.out <<= breg.x

操作

• 逻辑运算
  • & and
  • | or
  • ^ xor
  • ~ not
• exp[5:1] Extract bit field