1 -- IDDR2: Input Double Data Rate Input Register with Set, Reset 2 -- and Clock Enable. 3 -- Spartan-3A 4 -- Xilinx HDL Language Template, version 14.1 5 6 IDDR2_inst : IDDR2 7 generic map( 8 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 9 INIT_Q0 => '0', -- Sets initial state of the Q0 output to '0' or '1' 10 INIT_Q1 => '0', -- Sets initial state of the Q1 output to '0' or '1' 11 SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset 12 port map ( 13 Q0 => Q0, -- 1-bit output captured with C0 clock 14 Q1 => Q1, -- 1-bit output captured with C1 clock 15 C0 => C0, -- 1-bit clock input 16 C1 => C1, -- 1-bit clock input 17 CE => CE, -- 1-bit clock enable input 18 D => D, -- 1-bit data input 19 R => R, -- 1-bit reset input 20 S => S -- 1-bit set input 21 );
1 -- ODDR2: Output Double Data Rate Output Register with Set, Reset 2 -- and Clock Enable. 3 -- Spartan-3A 4 -- Xilinx HDL Language Template, version 14.1 5 6 ODDR2_inst : ODDR2 7 generic map( 8 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 9 INIT => '0', -- Sets initial state of the Q output to '0' or '1' 10 SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset 11 port map ( 12 Q => Q, -- 1-bit output data 13 C0 => C0, -- 1-bit clock input 14 C1 => C1, -- 1-bit clock input 15 CE => CE, -- 1-bit clock enable input 16 D0 => D0, -- 1-bit data input (associated with C0) 17 D1 => D1, -- 1-bit data input (associated with C1) 18 R => R, -- 1-bit reset input 19 S => S -- 1-bit set input 20 );