请到这个网站下载verilog加亮语法的文档。
http://www.ultraedit.com/downloads/extras.html
然后按下面步骤完成：
http://www.ultraedit.com/support/tutorials_power_tips/ultraedit/add_a_wordfile.html
Adding a wordfile
We are frequently asked if we can add support for a given language. The answer to this question is, UltraEdit-32's syntax highlighting is user configurable based on the wordfile. Therefore, if you can append to your wordfile, you can add syntax highlighting support for your desired language. You may have highlighting for as many as 20 languages specified in your wordfile.
We have user-submitted wordfiles available for download here. The following steps will guide you through appending to your wordfile.
Adding a Wordfile
You can find/open your default wordfile by going to Advanced : Configuration : Editor Display : Syntax Highlighting and clicking 'Open' (in the 'Full path name for wordlist' field).
（从菜单栏的 ->高级->配置->编辑器想显示->语法着色)
Open the downloaded wordfile in UltraEdit.
If you have not downloaded a wordfile yet, please do this now. You can download wordfiles here.
After you have opened the wordfile in UltraEdit, copy the entire contents of the new wordfile.
Go back to the default wordfile, which was already opened in UltraEdit, and Paste the contents of the clipboard (the downloaded wordfile) at the end of the default wordfile.
Please make sure that the wordfile you just pasted to the default wordfile does not have a duplicate language number.
The language is specified by a /Ln where n has a value of 1 to 20. This is at the beginning of the line.
Save the file using File : Save, or CTRL + S.
Any files opened after saving the modified wordfile, which have an extension matching those defined in the wordfile, will be highlighted accordingly.
在网上查了资料后，自定义了一个Verilog的环境，现在心得总结如下：
1：下载Verilog的语法高亮文件。
即可支持相应的语言编辑，关键字将用不同色彩标出。
2：将下载的文件打开，将里面的内容复制到WordFile.txt文件中（在UltraEdit的安装目录下），一般加在最后。
UltraEdit默认只有20种语法，将下载的文件的第一行“L20”改成你想要的序号，如L19。
3：加入折叠功能
由于Verilog HDL的块一般是以begin和end作为开始和结束的标记，其作用相当于C语言的
大括号。在wordfile.txt的对应语言中添加进如下代码即可：
/Open Fold Strings = "begin""case"
/Close Fold Strings = "end""endcase"
这里除了begin和end可以进行折叠外，另外一对case和endcase同样可以完成折叠，同样的
方法可以添加你需要的折叠标志。
4：加入自动缩进功能
同样在wordfile.txt中，有控制自动缩进的语法。所谓自动缩进就是指，输入begin回车，下一行自动加一个tab；输入end，下一行自动退回一个tab。用户可以自己添加不同的缩进词实现自动缩进。如：
/Indent Strings = "begin""case""fork" "if" "else"
/Unindent Strings = "end""endcase""join" "else"
5: 还可以加入其它一些自定义功能，如函数调用功能，大家可以自己摸索。
v14以前版本可直接粘贴下面的到wordfile中
/L16 Line Comment = // Block Comment On = /* Block Comment Off = */ String Chars = " File Extensions = V VMD
/Delimiters = ~!@%^&*()-+=|\/{}[]:;"<> , .?
/Function String = "%[a-z0-9]+[ ^t]+[a-z_0-9]+[ ^t]+("
/C1
always and assign
begin buf bufif0 bufif1
case casex casez cmos
deassign default defparam disable
edge else end endcase endmodule endfunction endprimitive endspecify endtable endtask event
for force forever fork function
highz0 highz1
if initial inout input integer
join
large Library
macromodule medium module
nand negedge nmos nor not notif0 notif1
or output
parameter pmos posedge primitive pull0 pull1 pullup pulldown
rcmos reg release repeat rnmos rpmos rtran rtranif0 rtanif1
scalared small specify specparam strength strong0 strong1 supply0 supply1
table task time tran tranif0 tranif1 tri1 tri0 triand trior trireg
vectored
wait wand weak0 weak1 while wire wor
xnor xor
/C2
$bitstoreal $countdrivers $display $fclose $fdisplay $finish $fmonitor $fopen $fstrobe $fwrite $finish $getpattern $history $hold $incsave $input $itor $key $list $log $monitor $monitoroff $monitoron $nokey $nolog $period $printtimescale $readmemb $readmemh $realtime $realtobits $recovery $reset $reset_count $reset_value $restart $rtoi $save $scale $scope $setup $setuphold $showscopes $showvariables $showvars $skew $sreadmemb $sreadmemh $stime $stop $strobe $time $timeformat $width $write
** 'b 'd 'h
/C3
`accelerate `autoexepand_vectornets `celldefine `default_nettype `define `else `endcelldefine `endif `endprotect `endprotected `expand_vectornets `ifdef `include `noaccelerate `noexpand_vectornets `noremove_gatenames `noremove_netnames `nounconnected_drive `protect `protected `remove_gatenames `remove_netnames `resetall `timescale `unconnected_drive
accelerate autoexepand_vectornets
celldefine
default_nettype define
else endcelldefine endif endprotect endprotected expand_vectornets
ifdef include
noaccelerate noexpand_vectornets noremove_gatenames noremove_netnames nounconnected_drive
protect protected
remove_gatenames remove_netnames resetall
timescale
unconnected_drive
,
;
{
}
+
-
*
/
%
> >= >>
< <= <<
! != !==
& &&
| ||
== ===
^ ^~
~ ~^ ~& ~|
?
:
#
@
/L17"Verilog 1364-2001" Line Comment = // Block Comment On = /* Block Comment Off = */ String Chars = " File Extensions = V VL VMD
/Delimiters = ~!@%^&*()-+=|\/{}[]:;"<> , .?#
/Function String = "%[a-z0-9]+[ ^t]+[a-z_0-9]+[ ^t]+("
/Indent Strings = "begin" "fork" "specify" "config"
/Unindent Strings = "end" "join" "endspecify" "endconfig"
/C1"Keywords"
always and assign automatic
begin buf bufif0 bufif1
case casex casez cell cmos config
deassign default defparam design disable
edge else end endcase endconfig endmodule endfunction endgenerate endprimitive endspecify endtable endtask event
for force forever fork function
generate genvar
highz0 highz1
if ifnone initial inout input instance integer
join
large liblist library localparam
macromodule medium module
nand negedge nmos none nor noshowcancelled not notif0 notif1
or output
parameter pulsestyle_onevent pulsestyle_ondetect pmos posedge primitive pull0 pull1 pullup pulldown
real realtime reg release repeat rcmos rnmos rpmos rtran rtranif0 rtanif1
scalared showcancelled signed small specify specparam strength strong0 strong1 supply0 supply1
table task time tran tranif0 tranif1 tri tri1 tri0 triand trior trireg
use
vectored
wait wand weak0 weak1 while wire wor
xnor xor
/C2"System"
** 'b 'B 'o 'O 'd 'D 'h 'H 'sb 'sB 'so 'sO 'sd 'sD 'sh 'sH 'Sb 'SB 'So 'SO 'Sd 'SD 'Sh 'SH
** _
$async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane
$bitstoreal
$countdrivers
$display $displayb $displayh $displayo
$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform
$dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars
$fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite
$getpattern
$history $hold
$incsave $input $itor
$key
$list $log
$monitorb $monitorh $monitoroff $monitoron $monitor $monitoro
$nochange $nokey $nolog
$period $printtimescale
$q_add $q_exam $q_full $q_initialize $q_remove
$random $readmemb $readmemh $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi
$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane
$test$plusargs $time $timeformat $timeskew
$ungetc $unsigned
$value$plusargs
$width $writeb $writeh $write $writeo
/C3"Operators"
->
+:
-:
@
@*
*>
,
;
{
}
+
-
// /
*
**
%
>
>=
>>
>>>
<
<=
<<
<<<
!
!=
!==
&
&&
|
||
=
==
===
^
^~
~
~^
~&
~|
?
:
/C4"Directives"
** `
`accelerate `autoexepand_vectornets
`celldefine
`default_nettype `define `default_decay_time `default_trireg_strength `delay_mode_distributed `delay_mode_path `delay_mode_unit `delay_mode_zero
`else `elsif `endcelldefine `endif `endprotect `endprotected `expand_vectornets
`file
`ifdef `ifndef `include
`line
`noaccelerate `noexpand_vectornets `noremove_gatenames `noremove_netnames `nounconnected_drive
`protect `protected
`remove_gatenames `remove_netnames `resetall
`timescale
`unconnected_drive `undef `uselib
/C5"DelaysAndParameters"
#