• 用于RISC-V的Makefile示例


    # Initialize ASM For RISC-V
     
    .section .text.entry
    .option norvc
    .global _start
     
    .macro push_reg
        addi sp, sp, -32*4
        sw x1, 0 * 4(sp)
        sw x2, 1 * 4(sp)
        sw x3, 2 * 4(sp)
        sw x4, 3 * 4(sp)
        sw x5, 4 * 4(sp)
        sw x6, 5 * 4(sp)
        sw x7, 6 * 4(sp)
        sw x8, 7 * 4(sp)
        sw x9, 8 * 4(sp)
        sw x10, 9 * 4(sp)
        sw x11, 10 * 4(sp)
        sw x12, 11 * 4(sp)
        sw x13, 12 * 4(sp)
        sw x14, 13 * 4(sp)
        sw x15, 14 * 4(sp)
        sw x16, 15 * 4(sp)
        sw x17, 16 * 4(sp)
        sw x18, 17 * 4(sp)
        sw x19, 18 * 4(sp)
        sw x20, 19 * 4(sp)
        sw x21, 20 * 4(sp)
        sw x22, 21 * 4(sp)
        sw x23, 22 * 4(sp)
        sw x24, 23 * 4(sp)
        sw x25, 24 * 4(sp)
        sw x26, 25 * 4(sp)
        sw x27, 26 * 4(sp)
        sw x28, 27 * 4(sp)
        sw x29, 28 * 4(sp)
        sw x30, 29 * 4(sp)
        sw x31, 30 * 4(sp)
        csrr t0, mepc
        sw t0, 31 * 4(sp)
    .endm
     
    .macro pop_reg
        lw t0, 31 * 4(sp)
        csrw mepc, t0
        lw x1, 0 * 4(sp)
        lw x2, 1 * 4(sp)
        lw x3, 2 * 4(sp)
        lw x4, 3 * 4(sp)
        lw x5, 4 * 4(sp)
        lw x6, 5 * 4(sp)
        lw x7, 6 * 4(sp)
        lw x8, 7 * 4(sp)
        lw x9, 8 * 4(sp)
        lw x10, 9 * 4(sp)
        lw x11, 10 * 4(sp)
        lw x12, 11 * 4(sp)
        lw x13, 12 * 4(sp)
        lw x14, 13 * 4(sp)
        lw x15, 14 * 4(sp)
        lw x16, 15 * 4(sp)
        lw x17, 16 * 4(sp)
        lw x18, 17 * 4(sp)
        lw x19, 18 * 4(sp)
        lw x20, 19 * 4(sp)
        lw x21, 20 * 4(sp)
        lw x22, 21 * 4(sp)
        lw x23, 22 * 4(sp)
        lw x24, 23 * 4(sp)
        lw x25, 24 * 4(sp)
        lw x26, 25 * 4(sp)
        lw x27, 26 * 4(sp)
        lw x28, 27 * 4(sp)
        lw x29, 28 * 4(sp)
        lw x30, 29 * 4(sp)
        lw x31, 30 * 4(sp)
        addi sp, sp, 32*4
    .endm
     
    .option norvc
     
    _start:
        j handle_reset
     
    trap_vector:
        j RVDefaultHandler
        j RVDefaultHandler   // 1
        j RVDefaultHandler   // 2
        j RVDefaultHandler   // 3
        j RVDefaultHandler   // 4
        j RVDefaultHandler   // 5
        j RVDefaultHandler   // 6
        j RVDefaultHandler   // 7
        j RVDefaultHandler   // 8
        j RVDefaultHandler   // 9
        j RVDefaultHandler   // 10
        j RVDefaultHandler   // 11
        j RVDefaultHandler   // 12
        j RVDefaultHandler   // 13
        j RVDefaultHandler   // 14
        j RVDefaultHandler   // 15
        j RVDefaultHandler   // 16
        j RVDefaultHandler   // 17
        j RVDefaultHandler   // 18
        j RVDefaultHandler   // 19
        j RVDefaultHandler   // 20
        j RVDefaultHandler   // 21
        j RVDefaultHandler   // 22
        j RVDefaultHandler   // 23
        j RVDefaultHandler   // 24
        j RVDefaultHandler   // 25
     
    RVDefaultHandler:
        j RVDefaultHandler
     
    .section .text
    .option norvc
     
    handle_reset:
        la t0, trap_vector
        addi t0, t0, 1
        csrw mtvec, t0
        csrwi mstatus, 0
        csrwi mie, 0
        la gp, _gp
        la sp, __stack_top
     
    # clear bss section
    clear_bss:
        la t0, __bss_begin
        la t1, __bss_end
        li t2, 0x00000000
     
    clear_bss_loop:
        sw      t2, (t0)
        addi    t0, t0, 4
        blt     t0, t1, clear_bss_loop
     
    jump_to_main:
        j main
     
     
    OUTPUT_ARCH("riscv")
    ENTRY(_start)
     
    MEMORY
    {
        RAM (rwx) : ORIGIN = 0x0, LENGTH = 8K
    }
     
    STACK_SIZE  = 2k;
    HEAP_SIZE   = 2k;
     
    SECTIONS
    {
        .text : ALIGN(4)
        {
            __start_addr = .;
            KEEP(*(.text.entry))
            . = ALIGN(4);
            *(.text*)
            . = ALIGN(4);
           __text_end = .;
        } > RAM
     
        .data :
        {
            __data_load = LOADADDR(.data);
            __rodata_start = .;
            *(.rodata*)
            . = ALIGN(4);
            __rodata_end = .;
            __data_start = .;
            *(.data*)
            . = ALIGN(4);
            __data_end = .;
        } > RAM
     
        .sdata :
        {
            __sdata_load = LOADADDR(.sdata);
            __sdata_start = .;
            _gp = . + 0x100;
            *(.srodata*)
            *(.sdata*)
            __sdata_end = .;
        } > RAM
     
        .bss : ALIGN(4)
        {
            __bss_begin = .;
     
            *(.sbss*)
            *(.scommon)
            *(.bss*)
            *(COMMON)
            . = ALIGN(4);
            __bss_end = .;
        } > RAM
        _end = .;
     
        .stack : ALIGN(4)
        {
            __stack_bottom = .;
            . += STACK_SIZE;
            __stack_top = .;
        } > RAM
     
        .heap : ALIGN(4)
        {
            __heap_begin = .;
            . += HEAP_SIZE;
            __heap_end = .;
        } > RAM
    }
    
    #***********************************************************************************************
    #    File        : Makefile
    #    Author      : Lyu Yang
    #    Date        :
    #    Description : Makefile for RISC-V
    #***********************************************************************************************
    
    TARGET = app_test
    
    CROSS_COMPILE = riscv64-unknown-elf-
    
    SRC_DIR = .
    OBJ_DIR = obj
    INC_DIR = -I ./
    LIB_DIR = -L ./
    
    CC = $(CROSS_COMPILE)gcc
    CFLAGS =  $(INC_DIR) -c -mabi=ilp32 -march=rv32i -Wall -O1 -std=c99 -gdwarf-2 -freorder-blocks-algorithm=simple -fno-schedule-insns -fno-aggressive-loop-optimizations -fno-builtin -Wstrict-prototypes -Wno-write-strings -fno-exceptions -fno-short-enums -Wundef -falign-functions=2 -fdata-sections -ffunction-sections -fno-common
    
    CXX = $(CROSS_COMPILE)g++
    CXXFLAGS =  $(INC_DIR) -c -mabi=ilp32 -march=rv32i -Wall -O1 -std=c99 -gdwarf-2 -freorder-blocks-algorithm=simple -fno-schedule-insns -fno-aggressive-loop-optimizations -fno-builtin -Wstrict-prototypes -Wno-write-strings -fno-exceptions -fno-short-enums -Wundef -falign-functions=2 -fdata-sections -ffunction-sections -fno-common
    
    AS = $(CROSS_COMPILE)gcc
    ASFLAGS = -c -mabi=ilp32 -march=rv32i -x assembler-with-cpp -Wall -O1 -gdwarf-2 -fstack-protector -fno-common -fdata-sections -ffunction-sections
    
    LD = $(CROSS_COMPILE)gcc
    LDFLAGS = $(LIB_DIR) -mabi=ilp32 -march=rv32i -nostartfiles -Triscv.lds -Wl,-Map,$(TARGET).map
    
    OBJCP = $(CROSS_COMPILE)objcopy
    OBJCPFLAGS = -O binary -j .text -j .data -j .sdata
    
    AR = $(CROSS_COMPILE)ar
    ARFLAGS = cr
    
    OBJDUMP = $(CROSS_COMPILE)objdump
    OBJDUMPFLAG = --disassemble --syms --all-header
    
    SIZE = $(CROSS_COMPILE)size
    
    ASMS = $(wildcard $(SRC_DIR)/*.S)
    SRCS = $(wildcard $(SRC_DIR)/*.c)
    
    OBJS += $(ASMS:$(SRC_DIR)/%.S=$(OBJ_DIR)/%.o)
    OBJS += $(SRCS:$(SRC_DIR)/%.c=$(OBJ_DIR)/%.o)
    DEPS += $(OBJS:%.o=%.d)
    
    # Make
    all: $(TARGET).elf $(TARGET).bin $(TARGET).asm $(TARGET).mif
    	$(SIZE) $(TARGET).elf
    
    $(OBJ_DIR)/%.o: $(SRC_DIR)/%.S
    	@mkdir -p $(shell dirname $@)
    	@$(AS) $(ASFLAGS) $< -o $@
    	@echo AS $<
    
    $(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
    	@mkdir -p $(shell dirname $@)
    	@$(CC) $(CFLAGS) -MM -MT $@ -MF $(patsubst %.o, %.d, $@) $<
    	@$(CC) $(CFLAGS) $< -o $@
    	@echo CC $<
    
    -include $(DEPS)
    
    $(TARGET).elf: $(OBJS)
    	@$(LD) $(LDFLAGS) $^ -o $@
    
    $(TARGET).asm: $(TARGET).elf
    	@$(OBJDUMP) $(OBJDUMPFLAG) $(TARGET).elf > $(TARGET).asm
    
    $(TARGET).bin: $(TARGET).elf
    	@$(OBJCP) $(OBJCPFLAGS) $< $@
    
    $(TARGET).mif: $(TARGET).bin
    	@./bin2fpga/bin2fpga 4096 $< > $(TARGET).txt
    
    clean:
    	@rm -rf obj $(TARGET).elf $(TARGET).map $(TARGET).asm $(TARGET).bin
    
    debug:
    	$(CROSS_COMPILE)gdb $(TARGET).elf -x gdbinit.txt
    

      

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  • 原文地址:https://www.cnblogs.com/lyuyangly/p/11149404.html
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