基于modelsim搭建的uvm仿真环境
set UVM_DPI_HOME C:/modeltech64_10.2c/uvm-1.1d/win64
set UVM_HOME C:/modeltech64_10.2c/verilog_src/uvm-1.1d
set CODE_PATH G:/05_uvm/Helloword/Helloword03
vlib work
vmap work work
vlog +incdir+$UVM_HOME/src+incdir+$CODE_PATH -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF $CODE_PATH/hello_world_example.sv
vsim -ldflags "-lregex" -c -novopt -sv_lib $UVM_DPI_HOME/uvm_dpi work.hello_world_example
`include "uvm_pkg.sv"
module hello_world_example;
import uvm_pkg::*;
`include "uvm_macros.svh"
initial begin
`uvm_info ("info1","Hello World!", UVM_LOW)
`uvm_info ("info2","Hello World!", UVM_LOW)
`uvm_info ("info3","Hello World!", UVM_LOW)
`uvm_info ("info4","Hello World!", UVM_LOW)
end
endmodule: hello_world_example