转载请注明原地址：http://www.cnblogs.com/connorzx/p/3674178.html
调时电路正常工作。一切正常。发现做FPGA还是得从数电的思路思考，设置一个预置使能端，预置数一直都可以设置。
代码
1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 use IEEE.STD_LOGIC_ARITH.ALL; 4 use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 6 entity clock is 7 Port ( clk : in STD_LOGIC; 8 btn0: in STD_LOGIC; 9 btn1: in STD_LOGIC; 10 load: in STD_LOGIC; 11 led0: out STD_LOGIC; 12 seg : out STD_LOGIC_VECTOR (6 downto 0); 13 seg7:out STD_LOGIC; 14 an : out STD_LOGIC_VECTOR (3 downto 0)); 15 end clock; 16 17 architecture Behavioral of clock is 18 signal num:STD_LOGIC_VECTOR (3 downto 0); 19 signal hour_h:STD_LOGIC_VECTOR (3 downto 0); 20 signal hour_l:STD_LOGIC_VECTOR (3 downto 0); 21 signal min_h:STD_LOGIC_VECTOR (3 downto 0); 22 signal min_l:STD_LOGIC_VECTOR (3 downto 0); 23 signal second_h:STD_LOGIC_VECTOR (3 downto 0); 24 signal second_l:STD_LOGIC_VECTOR (3 downto 0); 25 signal hour_l_t:STD_LOGIC_VECTOR (3 downto 0); 26 signal hour_h_t:STD_LOGIC_VECTOR (3 downto 0); 27 signal min_l_t:STD_LOGIC_VECTOR (3 downto 0); 28 signal min_h_t:STD_LOGIC_VECTOR (3 downto 0); 29 signal an_sel:STD_LOGIC_VECTOR (1 downto 0); 30 signal cnt: INTEGER; 31 signal cnt1: INTEGER; 32 signal cnt2: INTEGER; 33 signal cnt3: INTEGER; 34 signal sclk: STD_LOGIC; 35 signal aclk: STD_LOGIC; 36 signal shine:STD_LOGIC; 37 begin 38 led0<=shine; 39 process(clk) 40 begin 41 if(clk'event and clk='1') then 42 if(cnt=25000000) then 43 cnt<=0; 44 sclk<=not sclk; 45 else 46 cnt<=cnt+1; 47 end if; 48 end if; 49 end process; 50 51 process(clk) 52 begin 53 if(clk'event and clk='1') then 54 if(cnt2=50000) then 55 cnt2<=0; 56 if(an_sel="11") then 57 an_sel<="00"; 58 else 59 an_sel<=an_sel+'1'; 60 end if; 61 else 62 cnt2<=cnt2+1; 63 end if; 64 end if; 65 end process; 66 67 process(load,clk,btn0,btn1) 68 begin 69 if(load='1')then 70 if(clk'event and clk='1') then 71 if(btn0='1') then 72 if(cnt1=5000000) then 73 cnt1<=0; 74 if(hour_h_t="0010" and hour_l_t="0011" ) then 75 hour_h_t<="0000"; 76 hour_l_t<="0000"; 77 elsif(hour_l_t="1001")then 78 hour_h_t<=hour_h_t+'1'; 79 hour_l_t<="0000"; 80 else 81 hour_l_t<=hour_l_t+'1'; 82 end if; 83 else 84 cnt1<=cnt1+1; 85 end if; 86 elsif(btn1='1')then 87 if(cnt3=5000000) then 88 cnt3<=0; 89 if(min_h_t="0101" and min_l_t="1001" ) then 90 min_h_t<="0000"; 91 min_l_t<="0000"; 92 elsif(min_l_t="1001")then 93 min_h_t<=min_h_t+'1'; 94 min_l_t<="0000"; 95 else 96 min_l_t<=min_l_t+'1'; 97 end if; 98 else 99 cnt3<=cnt3+1; 100 end if; 101 end if; 102 end if; 103 end if; 104 end process; 105 106 process(sclk,load) 107 begin 108 if(load='1') then 109 min_l<=min_l_t; 110 min_h<=min_h_t; 111 hour_l<=hour_l_t; 112 hour_h<=hour_h_t; 113 else 114 if(sclk'event and sclk='1') then 115 shine<=second_l(0); 116 if(second_h="0101" and second_l="1001") then 117 second_h<="0000"; 118 second_l<="0000"; 119 min_l<=min_l+'1'; 120 if(min_h="0101" and min_l="1001") then 121 min_h<="0000"; 122 min_l<="0000"; 123 hour_l<=hour_l+'1'; 124 if(hour_h="0010" and min_l="0011") then 125 hour_h<="0000"; 126 hour_l<="0000"; 127 elsif(hour_l="1001")then 128 hour_h<=hour_h+'1'; 129 hour_l<="0000"; 130 end if; 131 elsif(min_l="1001") then 132 min_h<=min_h+'1'; 133 min_l<="0000"; 134 end if; 135 elsif(second_l="1001") then 136 second_h<=second_h+'1'; 137 second_l<="0000"; 138 else 139 second_l<=second_l+'1'; 140 end if; 141 end if; 142 end if; 143 end process; 144 145 process(an_sel,second_l,second_h,min_l,min_h,hour_l,hour_h) 146 begin 147 case an_sel is 148 when "00"=>an<="0111";num<=min_l;seg7<='1'; 149 when "01"=>an<="1011";num<=min_h;seg7<='1'; 150 when "10"=>an<="1101";num<=hour_l;seg7<='0'; 151 when "11"=>an<="1110";num<=hour_h;seg7<='1'; 152 when others=>null; 153 end case; 154 case num is 155 when x"0"=>seg<=b"0000001"; 156 when x"1"=>seg<=b"1001111"; 157 when x"2"=>seg<=b"0010010"; 158 when x"3"=>seg<=b"0000110"; 159 when x"4"=>seg<=b"1001100"; 160 when x"5"=>seg<=b"0100100"; 161 when x"6"=>seg<=b"0100000"; 162 when x"7"=>seg<=b"0001111"; 163 when x"8"=>seg<=b"0000000"; 164 when x"9"=>seg<=b"0000100"; 165 when others=>null; 166 end case; 167 end process; 168 end Behavioral;
约束文件
1 NET "clk" LOC = "B8"; 2 NET "led0" LOC ="M5"; 3 NET "an<0>" LOC="K14"; 4 NET "an<1>" LOC="M13"; 5 NET "an<2>" LOC="J12"; 6 NET "an<3>" LOC="F12"; 7 NET "seg7" LOC="N13"; 8 NET "seg<6>" LOC="L14"; 9 NET "seg<5>" LOC="H12"; 10 NET "seg<4>" LOC="N14"; 11 NET "seg<3>" LOC="N11"; 12 NET "seg<2>" LOC="P12"; 13 NET "seg<1>" LOC="L13"; 14 NET "seg<0>" LOC="M12"; 15 NET "btn1" LOC = "M4"; 16 NET "btn0" LOC = "A7"; 17 NET "load" LOC="P11";