• Shift Register(Using Submodule)


    /***************************************************

    /  Shift Register module by Submodule

    /  Programing by seongki

    ***************************************************/

    module Shift_Register_4_str(output [3:0] A_par,input [3:0] I_par,input s1,s0,MSB_in,LSB_in,CLK,Clear);

    wire [1:0] select;

    assign select = {s1,s0};

     

    stage ST0(I_par[0],I_par[1],LSB_in,I_par[0],A_par[0],select,CLK,Clear);

    stage ST1(I_par[1],I_par[2],I_par[0],I_par[1],A_par[1],select,CLK,Clear);

    stage ST2(I_par[2],I_par[3],I_par[1],I_par[2],A_par[2],select,CLK,Clear);

    stage ST3(I_par[3],MSB_in,I_par[2],I_par[3],A_par[3],select,CLK,Clear);

    endmodule

     

    module stage(i0,i1,i2,i3,Q,select,CLK,Clr);

    input i0,i1,i2,i3, CLK,Clr;

    output Q;

    input [1:0] select;

    wire mux_out;

    Mux_4x_1 M0(mux_out,i0,i1,i2,i3,select);

    D_flip_flop M1(Q,mux_out,CLK,Clr);

    endmodule

     

    module Mux_4x_1(mux_out,i0,i1,i2,i3,select);

    output mux_out;

    input i0,i1,i2,i3;

    input [1:0] select;

    reg mux_out;

    always@(select,i0,i1,i2,i3)

    case(select)

    2'b00:mux_out=i0;

    2'b01:mux_out=i1;

    2'b10:mux_out=i2;

    2'b11:mux_out=i3;

    endcase

    endmodule

     

    module D_flip_flop(Q,D,CLK,Clr);

    output Q;

    input D,CLK,Clr;

    reg Q;

    always@(posedge CLK, negedge Clr)

    if(~Clr) Q<=0;

    else Q<=D;

    endmodule

    //testbench

    `timescale 1ns/1ns

    module tb_Shift_Register_Structural_model;

    reg [3:0] I_par;

    reg s1,s0,MSB_in,LSB_in,CLK,Clear;

    wire [3:0] A_par;

     

    Shift_Register_4_str test1(A_par,I_par,s1,s0,MSB_in,LSB_in,CLK,Clear);

     

    initial

      begin

        I_par=4'b1111;

        Clear=0; MSB_in=0; LSB_in=0; CLK=0; s1=0; s0=0;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

        #10 CLK=1;

     

        #10 Clear=1; MSB_in=0; LSB_in=0; CLK=0; s1=0; s0=0;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

        #10 CLK=1;

     

        #10 Clear=1; MSB_in=0; LSB_in=0; CLK=0; s1=0; s0=1;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

        #10 CLK=1;

     

        #10 Clear=1; MSB_in=0; LSB_in=0; CLK=0; s1=1; s0=0;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

        #10 CLK=1;

     

        #10 Clear=1; MSB_in=0; LSB_in=0; CLK=0; s1=1; s0=1;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

        #10 CLK=1;

        #10 CLK=0;

     

      end

    endmodule

     

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  • 原文地址:https://www.cnblogs.com/capark/p/4004478.html
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