[转帖]信号处理知识

http://www.cnblogs.com/woshitianma/ 博客有许多跟我专业有关的，值得参考。

天马行空W   做想做的，做该做的——有思想就去实现！

verilog常用系统函数以及例子

来源：http://www.cnblogs.com/woshitianma/archive/2012/12/21/2828370.html

verilog常用系统函数以及例子

 

1.打开文件

　　integer file_id;

　　file_id = fopen("file_path/file_name");

2.写入文件：$fmonitor,$fwrite,$fdisplay,$fstrobe

　　//$fmonitor只要有变化就一直记录

　　$fmonitor(file_id, "%format_char", parameter);

　　$fmonitor(file_id, "%m: %t in1=%d o1=%h", $time, in1, o1);

//$fwrite需要触发条件才记录

　　$fwrite(file_id, "%format_char", parameter);

//$fdisplay需要触发条件才记录

　　$fdisplay(file_id, "%format_char", parameter);

$fstrobe();

3.读取文件：$fread

　　integer file_id;

　　file_id = $fread("file_path/file_name", "r");

4.关闭文件：$fclose

　　$fclose(fjile_id);

5.由文件设定存储器初值：$readmemh，$readmemb

　　$readmemh("file_name", memory_name"); //初始化数据为十六进制

　　$readmemb("file_name", memory_name"); //初始化数据为二进制

6、文件显示：$monitor,$write，$display

　$display,$write用于输出信息

　　$display("rvel = %h hex %d decimal",rvel,rvel);

　　$monitor($time, ,"rxd = %b txd = %b",rxd ,txd)

6、文件定位

　　$fseek，文件定位，可以从任意点对文件进行操作；

　　$fscanf，对文件一行进行读写。

7、退出仿真器$finish

8、随机数据产生：$random

下面是一些常见的应用：
        1、读写文件
`timescale 1 ns/1 ns
module FileIO_tb;
integer fp_r, fp_w, cnt;
reg [7:0] reg1, reg2, reg3;
initial begin
  fp_r = $fopen("data_in.txt", "r");
  fp_w = $fopen("data_out.txt", "w");
 
  while(!$feof(fp_r)) begin
    cnt = $fscanf(fp_r, "%d %d %d", reg1, reg2, reg3);
    $display("%d %d %d", reg1, reg2, reg3);
    $fwrite(fp_w, "%d %d %d
", reg3, reg2, reg1);
  end
 
  $fclose(fp_r);
  $fclose(fp_w);
end
endmodule
           2、
integer file, char;
reg eof;
initial begin
   file = $fopenr("myfile.txt");
   eof = 0;
   while (eof == 0) begin
       char = $fgetc(file);
       eof = $feof (file);
       $display ("%s", char); 
   end
end
        3、文件处理定位
`define SEEK_SET 0
`define SEEK_CUR 1
`define SEEK_END 2
integer file, offset, position, r;
r = $fseek(file, 0, `SEEK_SET);
r = $fseek(file, 0, `SEEK_CUR);
r = $fseek(file, 0, `SEEK_END);
r = $fseek(file, position, `SEEK_SET);
    　　4、
integer r, file, start, count;
reg [15:0] mem[0:10], r16;
r = $fread(file, mem[0], start, count);
r = $fread(file, r16);
       　　5、
integer file, position;
position = $ftell(file);
           6、
integer file, r, a, b;
reg [80*8:1] string;
file = $fopenw("output.log");
r = $sformat(string, "Formatted %d %x", a, b);
r = $sprintf(string, "Formatted %d %x", a, b);
r = $fprintf(file, "Formatted %d %x", a, b);
       7、
integer file, r;
file = $fopenw("output.log");
r = $fflush(file);
        8、
// This is a pattern file - read_pattern.pat
// time bin dec hex
10: 001 1 1
20.0: 010 20 020
50.02: 111 5 FFF
62.345: 100 4 DEADBEEF
75.789: XXX 2 ZzZzZzZz
`timescale 1ns / 10 ps
`define EOF 32'hFFFF_FFFF
`define NULL 0
`define MAX_LINE_LENGTH 1000

module read_pattern;
integer file, c, r;
reg [3:0] bin;
reg [31:0] dec, hex;
real real_time;
reg [8*`MAX_LINE_LENGTH:0] line;

initial
    begin : file_block
    $timeformat(-9, 3, "ns", 6);
    $display("time bin decimal hex");
    file = $fopenr("read_pattern.pat");
    if (file == `NULL) // If error opening file
        disable file_block; // Just quit

    c = $fgetc(file);
    while (c != `EOF)
        begin
       
        if (c == "/")
            r = $fgets(line, `MAX_LINE_LENGTH, file);
        else
            begin
            // Push the character back to the file then read the next time
            r = $ungetc(c, file);
            r = $fscanf(file," %f:
", real_time);

            // Wait until the absolute time in the file, then read stimulus
            if ($realtime > real_time)
                $display("Error - absolute time in file is out of order - %t",
                        real_time);
                else
                    #(real_time - $realtime)
                        r = $fscanf(file," %b %d %h
",bin,dec,hex);
                end // if c else
            c = $fgetc(file);
        end // while not EOF

    r = $fcloser(file);
    end // initial

// Display changes to the signals
always @(bin or dec or hex)
    $display("%t %b %d %h", $realtime, bin, dec, hex);

endmodule // read_pattern
        9、自动比较输出结果
`define EOF 32'hFFFF_FFFF
`define NULL 0
`define MAX_LINE_LENGTH 1000
module compare;
integer file, r;
reg a, b, expect, clock;
wire out;
reg [`MAX_LINE_LENGTH*8:1];
parameter cycle = 20;

initial
    begin : file_block
    $display("Time Stim Expect Output");
    clock = 0;

    file = $fopenr("compare.pat");
    if (file == `NULL)
        disable file_block;

    r = $fgets(line, MAX_LINE_LENGTH, file); // Skip comments
    r = $fgets(line, MAX_LINE_LENGTH, file);

    while (!$feof(file))
        begin
        // Wait until rising clock, read stimulus
        @(posedge clock)
        r = $fscanf(file, " %b %b %b
", a, b, expect);

        // Wait just before the end of cycle to do compare
        #(cycle - 1)
        $display("%d %b %b %b %b", $stime, a, b, expect, out);
        $strobe_compare(expect, out);
        end // while not EOF

    r = $fcloser(file);
    $stop;
    end // initial

always #(cycle / 2) clock = !clock; // Clock generator

and #4 (out, a, b); // Circuit under test
endmodule // compare
        10、从文件中读数据到mem（这个好像一般人用的最多了）
`define EOF 32'HFFFF_FFFF
`define MEM_SIZE 200_000
module load_mem;
integer file, i;
reg [7:0] mem[0:`MEM_SIZE];
reg [80*8:1] file_name;
initial    
begin    
file_name = "data.bin";    
file = $fopenr(file_name);    
i = $fread(file, mem[0]);    
$display("Loaded %0d entries 
", i);    
i = $fcloser(file);    
$stop;    
end endmodule // load_mem

MVI (Multimedia, Video, and Imaging) IP

来源：http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/bd-p/DSP

来源：http://www.xilinx.com/esp/video/refdes_listing.htm 可以下载参考实例

Deinterlacer, Video Scaler and Timing Controller

Real-Time Video Engine Targeted Reference Design

Reference Designs

Xilinx, Inc.

这个论坛很给力。

来源：https://avnetexpress.avnet.com/store/em/LogonForm?storeId=500201&catalogId=500201&URL=https://www.em.avnet.com/Support%20And%20Downloads/FMC_IMAGEON_Building_Video_Design_Tutorial_14_4_20130110.zip

video scaler IP -- vivado

来源：http://forums.xilinx.com/xlnx/board/crawl_message?board.id=DSP&message.id=3737

Video Scaler IP Core Problem when horizontal up-scale and vertical down-scale

Hi Everyone,

    Now I have problems about Video Scaler 7.01a in ISE 14.4 on spartan6 device. In most situations the scaler is working in the down-scale mode, and the output width and height are always less than the input width and height, and the scaler result is also correct. While in some situations such as convert 1024x768 to 1280x720, the horizontal direction is up scale while vertical direction is down scale, the scaler will work incorrectly and output image is uploaded in the attachment.

    While I also checked the scaler bit accurate C model, and the c model can handle YUV color format 1024x768 to 1280x720, and I need further work to check whether the c model can handle RGB color format 1024x768 to 1280x720. Mean while I'd like to know whether the problem is only related to scaler, not related to the C model

答案

I'm not completely sure what your design looks like, but the most common implemenation is to have a VDMA (Video Direct Memory Access) someplace after then Video Scaler.  This connects to memory, which typically runs at about 200MHz.  I would recommend that you just ty the core and output clocks to the 200MHz, reducing the number of clock domains in your design.

If you don't have this, then I would still recommend at least a 200MHz fixed core clock.  The reason is that when upscaing, the Video Scaler has to produce more data than it receives, and it needs time to do this.  And in addition there is some small amount of overhead for every line that has to be processed.  So for upscaling it is a good idea to give yourself some room and run the core clock slightly faster than the input clock.

Chris
Video Solutions Center: http://www.xilinx.com/support/answers/56851.htm

来源：http://wenku.baidu.com/view/bcda09c62cc58bd63186bdb3.html

数字滤波器要求输入、输出信号均为数字信号。

 数字滤波器（Digital Filter）通常是指一个用有限精度算法实现的离散线性时不变系统。因此它具有线性时不变系统的所有特性。

幅频响应表示信号通过该滤波器后各频率成分的衰减情况，而相频响应反映各频率成分通过滤波器后在时间上的延时情况。

多相滤波是将信号按照一定的规则分组，即抽取。同时将滤波器的冲击响应按照同样的规则分组，将对应的组进行卷积，得到一路的输出信号，最后将多路的信号重新排列得到输出信号。即先进行抽取再进行滤波，同传统的先滤波在抽取的滤波器比较多相滤波是一种很高效的滤波方式，因为传统的滤波在最后抽取的时候会丢掉很多没被抽取到但经过滤波的信号。同时多相滤波器每一路的运算量都大大减小，所以相对高效。

多相滤波过程式按照相位均匀划分把数字滤波器的系统函数H(z)分解成若干个具有不同相位的组，形成多个分支，在分支上实现滤波。

采用多相滤波结构，可利用多个阶数较低的滤波来实现原本阶数较高的滤波，而且每个分支滤波器处理的数据率仅为原数据率的I/D，这为工程上高速实时信号处理提供了实现途径。

来源：http://blog.sina.com.cn/s/blog_5d70c9e30101aiyi.html

线性相位滤波器

　1、相位随频率变化的曲线。它代表各频率分量在时间原点所具有的相位。

来源：http://zhidao.baidu.com/question/203285202.html?fr=qrl&index=0&qbl=topic_question_0&word=%B3%E9%CD%B7%20%CF%E0%CE%BB%20%C2%CB%B2%A8%C6%F7%CA%C7%CA%B2%C3%B4

滤波器的阶数，就是指过滤谐波的次数，一般来讲，同样的滤波器，其阶数越高，滤波效果就越好，但是，阶数越高，成本也就越高，因此，选择合适的阶数是非常重要的。

在我们描述一个滤波器时，会通过一组系数来确定滤波器的性能，用MATLAB的FDATOOL设计滤波器时，实际上就是我们设定参数，让它产生一组系数来实现，描述这个滤波器的系数的个数就是滤波器的长度，我们知道，滤波过程就是一个卷积过程，是让信号序列和这一组系数去卷积，滤波后的长度按卷积时的长度计算就是（信号序列长度+滤波器长度-1），这里讲的滤波器长度就应该是滤波器的系数个数。

滤波器，每一级都保存了一个经过延时的输入样值，各级的输入连接和输出连接被称为抽头。一个M 阶的FIR 滤波器将有M+1个抽头。