1、三态门指逻辑门电路的输出不仅有高电平、低电平，还有高阻态
它有一个使能控制端EN ，一个数据输入端DATAIN和一个数据输出端DATAOUT
2、单总线缓冲器
它通常由多个三态门组成，
3、双向总线缓冲器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity bidr_io1 is
port(mclk : in std_logic ;
rst_n : in std_logic;
mdata : inout std_logic_vector(15 downto 0);
sdata1: inout std_logic_vector( 7 downto 0);
cs_n : in std_logic;
wr_n : in std_logic;
rd_n : in std_logic
);
end bidr_io1;
architecture rtl of bidr_io1 is
signal mdatain ,mdataout : std_logic_vector(15 downto 0);
signal sdatain1,sdataout1: std_logic_vector( 7 downto 0);
signal trans_data : std_logic_vector(15 downto 0);
begin--从RTL视图中我们可以看到mdataout和sdataout1都没有综合
mdata <= mdataout when(rd_n = '0' and cs_n = '0') else ( others => 'Z');
mdatain <= mdata when( wr_n = '0' and cs_n = '0');
sdata1 <= sdataout1 when(wr_n = '0' and cs_n = '0') else ( others => 'Z');
sdatain1 <= sdata1 when(rd_n = '0' and cs_n = '0');
--=========================================================================
--在这里因为有一个位宽转换的原因，所以用到了补0函数EXT，
--如果两者位宽相同则可以用：mdataout <= sdatain1;
trans_data <= ext(sdatain1,16) ;--when (rd_n = '0' and cs_n = '0')
mdataout <= trans_data;
sdataout1 <= mdatain(7 downto 0);
end rtl;