occ实践

1.read_gate_and_protocol

read_ddc mapped/ORCA.ddc ;# note this was created during the unmapped flow
current_design ORCA
link

source -echo -verbose scripts/settings_protocol.tcl
create_test_protocol

dft_drc 

#step1 create port & eco
create_port ate_clk
disconnect_net [get_nets I_CLOCK_GEN/o_pclk] [get_pins I_CLOCK_GEN/o_pclk]  #断开网络o_plck与o_oclk这个pin得连接
connect_pin -from [get_pins I_CLOCK_GEN/I_PLL_PCI/CLK] -to [get_pins I_CLOCK_GEN/o_pclk]  #连接CLK pin和o_pclk pin

#step2 define signals
#specify test components in preparation for create_test_protocol
set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 40
set_dft_configuration -clock_controller enable
# specify the reference clock
set_dft_signal -view exist -type refclock -period 73 -timing {40 60} -port pclk
# specify the pll clock
set_dft_signal -view exist -type oscillator -hookup_pin I_CLOCK_GEN/I_PLL_PCI/CLK
# specify the ate clock
set_dft_signal -view exist -type oscillator -port ate_clk
set_dft_signal -view exist -type scanclock -timing {50 80} -port ate_clk
#set_dft_signal -view existing_dft -type ScanClock -timing {45 55} -port {pclk sdr_clk sys_clk}
set_dft_signal -view existing_dft -type ScanClock -timing {45 55} -port {sdr_clk sys_clk}
set_dft_signal -view existing_dft -port prst_n -type Reset -active_state 0
set_dft_signal -view spec -port scan_en -type ScanEnable -active_state 1
set_dft_signal -view existing_dft -type Constant -active_state 1 -port test_mode



# step3 Clock controller specifications
    set_dft_configuration -clock_controller enable
    set_dft_clock_controller -cell_name pll_controller -design_name snps_clk_mux 
                    -pllclocks {I_CLOCK_GEN/I_PLL_PCI/CLK} -ateclocks {ate_clk} -cycles_per_clock 4

2.preview_dft

source -echo -ver scripts/settings_insert_dft.tcl 
remove_test_protocol
create_test_protocol
dft_drc
preview_dft -show scan_summary

# This script insert the scan chains

# Scan synthesis and autofix settings
set_dft_insertion_configuration -synthesis none -preserve_design_name true
set_autofix_configuration -type bidirectional -method input

# allow clock domains to be mixed together on same chain

set_scan_configuration -chain_count 5 -add_lockup true -clock_mixing mix_clocks

# Specify all scan ports

for {set i 0} {$i < 5 } {incr i} {
    set hookup_cell pad_iopad_$i
    set_dft_signal -view spec -port pad[$i] -type ScanDataIn -hookup_pin $hookup_cell/CIN
    set hookup_cell sdram_A_iopad_$i
    set_dft_signal -view spec -port sd_A[$i] -type ScanDataOut -hookup_pin $hookup_cell/I
    set_scan_path chain$i -view spec -scan_data_in pad[$i] -scan_data_out sd_A[$i] 
}

#
### Enable Adaptive scan HERE
#
set_dft_configuration -scan_compression enable

#
### Specify compression ratio HERE
#
set_scan_compression_configuration -minimum_compression 5 

#
### Add TM_COMP port HERE
#
create_port -direction in TM_COMP
set_dft_signal -view spec -type TestMode -port TM_COMP

3.insert_dft

set compile_instance_name_prefix DFTC_
insert_dft
current_test_mode Internal_scan
dft_drc
current_test_mode ScanCompression_mode
dft_drc 

4handoff

#report_scan_configuration > reports/scan_config
report_scan_configuration -test_mode all > reports/scan_config
report_dft_signal -view existing_dft > reports/dft_signals
report_scan_path -view existing_dft -chain all > reports/scan_chains
report_scan_path -view existing_dft -cell all > reports/scan_cells

# hand off
set test_stil_netlist_format verilog
write -hierarchy -format verilog -output tmax/ORCA_COMP_scan.v
write -hierarchy -format ddc     -output mapped_scan/ORCA_COMP.ddc

# Write Internal_scan protocol:
write_test_protocol -out ./tmax/scan.spf 
  -test_mode Internal_scan

# Write ScanCompression_mode protocol:
write_test_protocol -out ./tmax/scancompress.spf 
  -test_mode ScanCompression_mode