https://www.cnblogs.com/yeungchie/
通过 si 导出电路网表，实际上在 Virtuoso 中通过菜单 File - Export - CDL 和 Calibre LVS 中 Export from schematic viewer 也是通过 si 来导出电路网表的，下面讲下如何使用。
如何运行 si
下面是 si 的运行命令， $cdslibFile 为 cds.lib 文件。
si -batch -command netlist -cdslib $cdslibFile
si.env 文件
在 si 的运行路径下需要提前准备好一个 si.env 文件，si 通过读取这个文件的内容来配置导出 cdl 所需要的信息。
文件的如何编写可以参考 help 文档：
- Virtuoso Shared Tools
- Design Data Translators Reference
- Design Translation Using CDL Out
- Using CDL Out
- Preparing the si.env File
- Using CDL Out
- Design Translation Using CDL Out
- Design Data Translators Reference
简单看看就行，我一般是直接通过 GUI 界面尝试导出一份 cdl，然后在运行路径下会有一份 si.env 文件，下面是一个例子：
simLibName = "stdcel"
simCellName = "TOP"
simViewName = "schematic"
simSimulator = "auCdl"
simNotIncremental = 't
simReNetlistAll = nil
simViewList = '("auCdl" "cdl" "schematic" "cmos_sch" "gate_sch" "cmos.sch" "gate.sch" "symbol")
simStopList = '("auCdl" "cdl")
hnlNetlistFileName = "TOP.cdl"
resistorModel = ""
shortRES = 2000.0
preserveRES = 't
checkRESVAL = 't
checkRESSIZE = 'nil
preserveCAP = 't
checkCAPVAL = 't
checkCAPAREA = 'nil
preserveDIO = 't
checkDIOAREA = 't
checkDIOPERI = 't
checkCAPPERI = 'nil
simPrintInhConnAttributes = 'nil
checkScale = "meter"
checkLDD = 'nil
pinMAP = 'nil
preserveBangInNetlist = 'nil
shrinkFACTOR = 0.0
globalPowerSig = ""
globalGndSig = ""
displayPININFO = 't
preserveALL = 't
setEQUIV = ""
incFILE = "./Subcircuit/3t_device.cdl"
auCdlDefNetlistProc = "ansCdlHnlPrintInst"
这个例子中导出的顶层电路单元是 stdcel/TOP/schematic，我们只关心其中几个常用的变量：
- simLibName ( Library Name )
stdcel - simCellName ( Top Cell Name )
TOP - simViewName ( View Name )
schematic - hnlNetlistFileName ( Output CDL Netlist File )
- incFILE ( Include File )
- auCdlDefNetlistProc ( Analog Netlisting Type )
这个变量决定 pin 的连接方式- ansCdlSubcktCall ( Connection By Order )
顺序连接 - ansCdlHnlPrintInst ( Connection By Name )
命名端口连接，一般选择这个来保证 IP/Digital 网表的连接
- ansCdlSubcktCall ( Connection By Order )
Run Directory 直接由 si 的运行路径来决定。
编写脚本 export_cdl
明白了 si 的使用方法，现在可以写一个 shell 脚本，在 Terminal 操作，实现便捷地导出指定电路单元的 cdl 文件。
点击查看完整代码
#!/bin/bash
#--------------------------
# Program : export_cdl.sh
# Language : Bash
# Author : YEUNGCHIE
# Version : 2022.04.03
#--------------------------
HelpInfo(){
cat <<EOF
-------------------------------------------------
Export CDL ( Circuit Description Language ) File
-------------------------------------------------
Usage: export_cdl -cdslib cdslibFile -lib libName -cell cellName [ OPTIONS ]
-cdslib Path of cds.lib file
-lib Schematic top cell libName
-cell Schematic top cell cellName
-view Schematic top cell viewName ( Default: schematic )
-file Output netlist file name ( Default: ./<cellName>.cdl )
-include Include subckt file name
-order Netlisting Type Connection By Order ( The default is By Name )
-h, -help Display this help
Examples: export_cdl -cdslib ./cds.lib -lib Xeon -cell X999 -include ./subckt.cdl
Output: Netlist file: X999.cdl
EOF
}
viewName='schematic'
connType='ansCdlHnlPrintInst'
# 命令行参数分析
while [[ -n $1 ]]; do
if [[ -n $opt ]]; then
case $opt in
lib_opt) libName=$1 ;;
cell_opt) cellName=$1 ;;
view_opt) viewName=$1 ;;
file_opt) netlistFile=$1 ;;
cdslib_opt) cdslibFile=$1 ;;
include_opt) includeFile=$1 ;;
esac
unset opt
else
case $1 in
-lib) opt='lib_opt' ;;
-cell) opt='cell_opt' ;;
-view) opt='view_opt' ;;
-file) opt='file_opt' ;;
-cdslib) opt='cdslib_opt' ;;
-include) opt='include_opt' ;;
-order)
connType='ansCdlSubcktCall'
;;
-h|-help)
HelpDoc >&2
exit 1
;;
*)
echo "Invalid option - '$1'" >&2
echo "Try -h or -help for more infomation." >&2
exit 1
;;
esac
fi
shift
done
# 参数检查
if [[ ! ( $cdslibFile && $libName && $cellName ) ]]; then
## 缺少必要参数时，打印 help 并退出
HelpInfo >&2
exit 1
elif [[ -f $cdslibFile ]]; then
## 将相对路径改为绝对路径
cdslibDir=$(cd $(dirname $cdslibFile); pwd -P)
fileName=$(basename $cdslibFile)
cdslibFile="$cdslibDir/$fileName"
else
## 找不到 cds.lib 文件，打印报错
echo "No such file - $cdslibFile" >&2
echo "Try -h or -help for more infomation." >&2
exit 1
fi
## 当网表文件名未定义时，设置默认文件名
if [[ ! $netlistFile ]]; then netlistFile="${cellName}.cdl" ; fi
# si.env 文件生成
cat > si.env <<EOF
simLibName = "$libName"
simCellName = "$cellName"
simViewName = "$viewName"
simSimulator = "auCdl"
simNotIncremental = 't
simReNetlistAll = nil
simViewList = '("auCdl" "cdl" "schematic" "cmos_sch" "gate_sch" "cmos.sch" "gate.sch" "symbol")
simStopList = '("auCdl" "cdl")
simNetlistHier = t
hnlNetlistFileName = "$netlistFile"
resistorModel = ""
shortRES = 2000.0
preserveRES = 't
checkRESVAL = 't
checkRESSIZE = 'nil
preserveCAP = 't
checkCAPVAL = 't
checkCAPAREA = 'nil
preserveDIO = 't
checkDIOAREA = 't
checkDIOPERI = 't
checkCAPPERI = 'nil
simPrintInhConnAttributes = 'nil
checkScale = "meter"
checkLDD = 'nil
pinMAP = 'nil
preserveBangInNetlist = 'nil
shrinkFACTOR = 0.0
globalPowerSig = ""
globalGndSig = ""
displayPININFO = 't
preserveALL = 't
setEQUIV = ""
incFILE = ""
auCdlDefNetlistProc = "$connType"
EOF
# 运行 si
si -batch -command netlist -cdslib $cdslibFile
status=$?
# 删除中间文件
if [[ -f .stimulusFile.auCdl ]]; then rm -rf .stimulusFile.auCdl ; fi
if [[ -f si.env ]]; then rm -rf si.env ; fi
if [[ -f netlist ]]; then rm -rf netlist ; fi
if [[ -d ihnl ]]; then rm -rf ihnl ; fi
if [[ -d map ]]; then rm -rf map ; fi
exit $status
运行实例
例：cdslib 文件为 ./cds.lib
-
导出
verify库中的ad01d0单元的电路网表。export_cdl -cdslib cds.lib -lib verify -cell ad01d0导出的 cdl 文件名为
ad01d0.cdl -
导出
verify库中的inv0d0单元的电路网表，同时包含 subckt 网表文件./netlist，并指定 cdl 文件名为inv.cdl。export_cdl -cdslib ./cds.lib -lib verify -cell inv0d0 -include ./netlist导出的 cdl 文件名为
inv.cdl