【iCore1S 双核心板_ARM】例程十七：FSMC实验——读写FPGA

实验现象：

先烧写FPGA程序，再烧写ARM程序，ARM程序烧写完毕后即开始读写RAM测试，测试成功，绿色ARM·LED亮，测试失败，红色ARM·LED闪烁。

核心代码：

int main(void)
{

  /* USER CODE BEGIN 1 */

  /* USER CODE END 1 */

  /* MCU Configuration----------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();

  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();

  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
  MX_FSMC_Init();

  /* USER CODE BEGIN 2 */
    int i;
    unsigned short int fsmc_read_data;
    LED_GREEN_ON;
    
    /*ÂÌÉ«ledÁÁ£¬±íʾ²âÊÔÕý³£
    ºìÉ«ledÁÁ£¬±íʾ²âÊÔʧ°Ü£¬²âÊÔ½áÊø*/

  /* USER CODE END 2 */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
  {
  /* USER CODE END WHILE */

  /* USER CODE BEGIN 3 */
        for(i = 0;i < 512;i++){
         fpga_write(i,i);                  //ÏòFPGAдÈëÊý¾Ý
        }    
        for(i = 0;i < 512;i++){
            fsmc_read_data = fpga_read(i);   //´ÓFPGA¶ÁÊý¾Ý
            if(fsmc_read_data != i){
                LED_GREEN_OFF;
                LED_RED_ON;
                while(1);
            }            
        }

  }
  /* USER CODE END 3 */

}

 module FSMC_Ctrl(
    ab,
    db,
    wrn,
    rdn,
    csn,
    PLL_100M,
    RST_n,
    nadv
     );
    
//-------------------------fsmc ------------------------------//    
    input [24:16]ab;
    inout [15:0]db;
    input wrn;
    input rdn;
    input csn;
    input PLL_100M;
    input RST_n; 
    input nadv;
    
    wire rd;
    wire wr;
    wire [15:0]DB_OUT;
//-------------------------rd_wr ----------------------------//        
    assign rd = (csn | rdn);
    assign wr = (csn | wrn);
            
//-------------------------ab ------------------------------//
    reg [24:0]address;
    always @ (posedge nadv or negedge RST_n)
        begin
            if(!RST_n)
                begin
                    address <= 25'd0;
                end
            else 
                begin
                    address <= {ab,db};
                end
        end 

//-------------------------clk ----------------------------//
    reg wr_clk1,wr_clk2;    
    always @(posedge PLL_100M or negedge RST_n)
        begin
            if(!RST_n)
                begin
                    wr_clk1 <= 1'd1;
                    wr_clk2 <= 1'd1;
                end
            else
                {wr_clk2,wr_clk1} <= {wr_clk1,wr};    //提取写时钟
        end
        
    wire clk = (!wr_clk2 | !rd);
    
//------------------------db_out -------------------------//    
    assign db = !rd ? DB_OUT : 16'hzzzz;

//------------------------ma_ram ------------------------//    
my_ram      u1(                                            //ram块例化
                    .address(address),
                    .clock(clk),
                    .data(db),
                    .wren(!wr),
                    .rden(!rd),
                    .q(DB_OUT),
                    );
                    
//-------------------------endmodule ------------------------------//
endmodule

实验方法及指导书:

链接：https://pan.baidu.com/s/1fN0LlFdfTBUqA7VeLMxieA
提取码：zbjj