【iCore1S 双核心板_FPGA】例程二：GPIO输入实验——识别按键输入

实验现象：

iCore1s 双核心板上与FPGA相连的三色LED（PCB上标示为FPGA·LED），按键按下红灯点亮，松开按键红灯熄灭。

核心源代码：

module KEY(
    input CLK_12M,
    input FPGA_KEY,
    output FPGA_LEDR,
    output FPGA_LEDG,
    output FPGA_LEDB
);
//----------------------rst_n-----------------------//
//产生复位信号    
    reg rst_n;
    reg [3:0]cnt_rst;
    
    always@(posedge CLK_12M)
        if(cnt_rst==4'd10)
            begin
                rst_n <= 1'd1;
                cnt_rst <= 4'd10;
            end
        else cnt_rst <= cnt_rst + 1'd1;
//-----------------------KEY_CLK--------------------//
//将按键的按下与松开转换为KEY_CLK,按下后松开为上升沿 
    reg KEY_CLK;
    reg [7:0]cnt_key0;
    reg [7:0]cnt_key1;
    always@(posedge CLK_12M or negedge rst_n )
        begin
            if(!rst_n)
                begin
                    KEY_CLK <= 1'd0;
                    cnt_key0 <= 8'd0;
                    cnt_key1 <= 8'd0;
                end
            else if(!FPGA_KEY)
                begin
                    cnt_key0 <= cnt_key0 + 1'd1;
                    if(cnt_key0==8'd200)//消抖
                        begin
                            
                            if(!FPGA_KEY)
                                begin
                                    KEY_CLK <= 1'd0;
                                    cnt_key0 <= 8'd0;
                                end
                        end                    
                end
            else if(FPGA_KEY)
                begin
                    cnt_key1 <= cnt_key1 + 1'd1;
                    if(cnt_key1==8'd200)//消抖
                        begin
                            if(FPGA_KEY)
                                begin
                                    KEY_CLK <= 1'd1;
                                    cnt_key1 <= 8'd0;
                                end
                        end
                end
        end
//-----------------------led-------------------------//    
    reg [1:0]led_state;
    reg ledr,ledg,ledb;

    always@(posedge KEY_CLK or negedge rst_n)
        begin
            if(!rst_n)
                begin
                    led_state <= -2'd1;//初始化使灯熄灭
                    ledr <= 1'd1;
                    ledg <= 1'd1;
                    ledb <= 1'd1;
                end    
            else 
                begin
                    led_state <= led_state + 1'd1;
                    if(led_state > 2'd2)
                        begin
                            led_state <= 2'd0;
                        end
                    case(led_state)
                        2'd0:            //红灯亮
                            begin
                                ledr <= 1'd0;
                                ledg <= 1'd1;
                                ledb <= 1'd1;
                            end
                        2'd1:            //绿灯亮
                            begin
                                ledr <= 1'd1;
                                ledg <= 1'd0;
                                ledb <= 1'd1;
                            end
                        2'd2:            //蓝灯亮
                            begin
                                ledr <= 1'd1;
                                ledg <= 1'd1;
                                ledb <= 1'd0;
                            end
                        default :    //灯熄灭
                            begin                    
                                ledr <= 1'd1;
                                ledg <= 1'd1;
                                ledb <= 1'd1;                    
                            end
                    endcase
                end    
        end
        
    assign FPGA_LEDR = ledr;
    assign FPGA_LEDG = ledg;
    assign FPGA_LEDB = ledb;
    
//--------------------endmodule------------------//    
endmodule 

代码包下载：

链接：http://pan.baidu.com/s/1kUWAJC7 密码：13jp