校招Verilog——单bit快慢时钟域切换（脉冲展宽法）

module Sync_Pulse
(
    input   clka,
    input   clkb,
    input   rst_n,
    input   pulse_ina,      //脉冲或电平信号都可以
    output  pulse_outb,     //脉冲信号
    output  signal_outb     //电平信号
);
//--------------------------------------------------------
reg         signal_a;
reg         signal_a_r1;
reg         signal_a_r2;
reg         signal_b;
reg         signal_b_r1;
//--------------------------------------------------------
//--    a时钟域生成展宽信号
//--------------------------------------------------------
always @(posedge clka or negedge rst_n)begin
    if(!rst_n)begin
        signal_a <= 1'b0;
    end
    else if(pulse_ina) begin        //检测到脉冲
        signal_a <= 1'b1;           //拉高
    end
    else if(signal_a_r2) begin      //同步到b后同步回a
        signal_a <= 1'b0;           //拉低，展宽使命完成
    end
end
//--------------------------------------------------------
//--    展宽信号同步到b时钟域再同步回a时钟域
//--------------------------------------------------------
always @(posedge clkb or negedge rst_n)begin
    if(!rst_n)begin
        signal_b    <= 1'b0;
        signal_b_r1 <= 1'b0;
    end
    else begin
        signal_b    <= signal_a;
        signal_b_r1 <= signal_b;
    end
end

always @(posedge clka or negedge rst_n)begin
    if(!rst_n)begin
        signal_a_r1 <= 1'b0;
        signal_a_r2 <= 1'b0;
    end
    else begin
        signal_a_r1 <= signal_b_r1;
        signal_a_r2 <= signal_a_r1;
    end
end
//--------------------------------------------------------
//--    脉冲信号输出,上升沿检测
//--------------------------------------------------------
assign pulse_outb = ~signal_b_r1 & signal_b;
//--------------------------------------------------------
//--    电平信号输出，b时钟域展宽信号
//--------------------------------------------------------
assign signal_outb = signal_b_r1;


endmodule

这个代码建议背出来，看不太懂就自己仿真看看吧！