blocking and nonblocking

module    sort3
(
    data_in1,data_in2,data_in3,
    data_out1,data_out2,data_out3,
    clk,reset
);

output    [7:0]        data_out1,data_out2,data_out3;
input        [7:0]        data_in1,data_in2,data_in3;
input                    clk,reset;

reg        [7:0]        data_out1,data_out2,data_out3;
reg        [7:0]        data_tempt1,data_tempt2,data_tempt3;

always @ (posedge clk)
    if(!reset)
        begin
            data_out1    <=    1'b0;
            data_out2    <=    1'b0;
            data_out3    <=    1'b0;
        end
    else
        begin
            {data_tempt1,data_tempt2,data_tempt3}={data_in1,data_in2,data_in3};
            sort2(data_tempt1,data_tempt2);
            sort2(data_tempt1,data_tempt3);
            sort2(data_tempt2,data_tempt3);
            {data_out1,data_out2,data_out3}={data_tempt1,data_tempt2,data_tempt3};
        end
        
task    sort2;
    inout        [7:0]        x,y;
    reg        [7:0]        temp;
    if(x > y)
        begin
            temp    =    x;
            x        =    y;                    //因为需要做数据交换，所以用blocking赋值
            y        =    temp;
        end
endtask

endmodule

数字排序，用到了blocking，仿真结果正确。

module    sort3
(
    data_in1,data_in2,data_in3,
    data_out1,data_out2,data_out3,
    clk,reset
);

output    [7:0]        data_out1,data_out2,data_out3;
input        [7:0]        data_in1,data_in2,data_in3;
input                    clk,reset;

reg        [7:0]        data_out1,data_out2,data_out3;
reg        [7:0]        data_tempt1,data_tempt2,data_tempt3;

always @ (posedge clk)
    if(!reset)
        begin
            data_out1    <=    1'b0;
            data_out2    <=    1'b0;
            data_out3    <=    1'b0;
        end
    else
        begin
            {data_tempt1,data_tempt2,data_tempt3}={data_in1,data_in2,data_in3};
            sort2(data_tempt1,data_tempt2);
            sort2(data_tempt1,data_tempt3);
            sort2(data_tempt2,data_tempt3);
            {data_out1,data_out2,data_out3}={data_tempt1,data_tempt2,data_tempt3};
        end
        
task    sort2;
    inout        [7:0]        x,y;
    reg        [7:0]        temp;
    if(x > y)
        begin
        temp        <=    x;
            x        <=    y;                    //因为需要做数据交换，所以用blocking赋值
            y        <=    temp;
        end
endtask

endmodule

 nonblocking仿真结果错误。

在编写时牢记这八个要点可以为绝大多数的
Verilog 用户解决在综合后仿真中出现的 90-100% 的冒险竞争问题。
1) 时序电路建模时，用非阻塞赋值。
2) 锁存器电路建模时，用非阻塞赋值。
3) 用 always 块建立组合逻辑模型时，用阻塞赋值。
4) 在同一个 always 块中建立时序和组合逻辑电路时，用非阻塞赋值。
5) 在同一个 always 块中不要既用非阻塞赋值又用阻塞赋值。
6) 不要在一个以上的 always 块中为同一个变量赋值。
7) 用$strobe 系统任务来显示用非阻塞赋值的变量值
8) 在赋值时不要使用 #0 延迟