• OpenHCI


    The Host Controller (HC) contains a set of on-chip operational registers which are mapped into a noncacheable portion of the system addressable space. These registers are used by the Host Controller Driver (HCD). According to the function of these registers, they are divided into four partitions, specifically for Control and Status, Memory Pointer, Frame Counter and Root Hub. All of the registers should be read and written as Dwords. 

    Reserved bits may be allocated in future releases of this specification. To ensure interoperability, the Host Controller Driver that does not use a reserved field should not assume that the reserved field contains 0. Furthermore, the Host Controller Driver should always preserve the value(s) of the reserved field. When a R/W register is modified, the Host Controller Driver should first read the register, modify the bits desired, then write the register with the reserved bits still containing the read value. Alternatively, the Host Controller Driver can maintain an in-memory copy of previously written values that can be modified and then written to the Host Controller register. When a write to set/clear register is written, bits written to reserved fields should be 0.

    Control and Status HcControl 0x04H The HcControl register defines the operating modes for the Host Controller.
    HcCommandStatus  0x08H The HcCommandStatus register is used by the Host Controller to receive commands issued by the Host Controller Driver, as well as reflecting the current status of the Host Controller.
    HcInterruptStatus 0x0CH This register provides status on various events that cause hardware interrupts.
    HcInterruptEnable 0x10H Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register.The HcInterruptEnable register is used to control which events generate a hardware interrupt.
    HcInterruptDisable 0x14H Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register.
    Memory Pointer HcHCCA 0x18H The HcHCCA register contains the physical address of the Host Controller Communication Area.
    HcPeriodCurrentED 0x1CH The HcPeriodCurrentED register contains the physical address of the current Isochronous or Interrupt Endpoint Descriptor.
    HcControlHeadED 0x20H The HcControlHeadED register contains the physical address of the first Endpoint Descriptor of the Control list.
    HcControlCurrentED 0x24H The HcControlCurrentED register contains the physical address of the current Endpoint Descriptor of the Control list.
    HcBulkHeadED 0x28H The HcBulkHeadED register contains the physical address of the first Endpoint Descriptor of the Bulk list.
    HcBulkCurrentED 0x2CH The HcBulkCurrentED register contains the physical address of the current endpoint of the Bulk list.
    HcDoneHead 0x30H The HcDoneHead register contains the physical address of the last completed Transfer Descriptor that was added to the Done queue.
    Frame Counter HcFmInterval 0x34H The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a Frame, (i.e., between two consecutive SOFs), and a 15-bit value indicating the Full Speed maximum packet size that the Host Controller may transmit or receive without causing scheduling overrun.
    HcFmRemaining 0x38H The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current Frame.
    HcFmNumber 0x3CH The HcFmNumber register is a 16-bit counter. It provides a timing reference among events happening in the Host Controller and the Host Controller Driver.
    HcPeriodicStart 0x40H The HcPeriodicStart register has a 14-bit programmable value which determines when is the earliest time HC should start processing the periodic list.
    HcLSThreshold 0x44H The HcLSThreshold register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF.
    Root Hub HcRhDescriptorA 0x48H The HcRhDescriptorA register is the first register of two describing the characteristics of the Root Hub.
    HcRhDescriptorB 0x4CH The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub.
    HcRhStatus 0x50H The HcRhStatus register is divided into two parts. The lower word of a Dword represents the Hub Status field and the upper word represents the Hub Status Change field.
    HcRhPortStatus[1] 0x54H The HcRhPortStatus[1:NDP] register is used to control and report port events on a per-port basis.
       
    HcRhPortStatus[NDP] 54+4*NDP  
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  • 原文地址:https://www.cnblogs.com/utank/p/4636421.html
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