Error (10773): Verilog HDL error at test.v(275): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions
是因为module的port不允许定义一个寄存器数组,如
module test(
render_rsn,
obj_property,
sclk,
rsn
);
reg [31:0] obj_property [9: 0];