ARM JTAG SWD SWO SWV

 

JTAG - Joint Test Action Group

JTAG(Joint Test Action Group)联合测试行动小组)是一种国际标准测试协议（IEEE 1149.1兼容）
Test Access Port and Boundary-Scan Architecture
主要用于芯片内部测试及对系统进行仿真、调试。现在多数的高级器件都支持JTAG协议，如DSP、FPGA器件等。通常所说的JTAG大致分两类，

一类用于测试芯片的电气特性，检测芯片是否有问题；
一类用于Debug；一般支持JTAG的CPU内都包含了这两个模块。

一个含有JTAG Debug接口模块的CPU，只要时钟正常，就可以通过JTAG接口访问CPU的内部寄存器和挂在CPU总线上的设备

标准的JTAG接口是4线：TMS、 TCK、TDI、TDO，分别为模式选择、时钟、数据输入和数据输出线。 

 

ARM系统的JTAG接口

 接口是一个20脚的IDC插座。下表给出了具体的信号说明

序号	信号名	方向	说 明
1	Vref	Input	接口电平参考电压，通常可直接接电源
2	Vsupply	Input	电源
3	nTRST	Output	(可选项) JTAG复位。在目标端应加适当的上拉电阻以防止误触发。
4	GND	--	接地
5	TDI	Output	Test Data In from Dragon-ICE to target.
6	GND	--	接地
7	TMS	Output	Test Mode Select
8	GND	--	接地
9	TCK	Output	Test Clock output from Dragon-ICE to the target
10	GND	--	接地
11	RTCK	Input	(可选项) Return Test Clock。由目标端反馈给Dragon-ICE的时钟信号，用来同步TCK信号的产生。不使用时可以直接接地。
12	GND	--	接地
13	TDO	Input	Test Data Out from target to Dragon-ICE.
14	GND	--	接地
15	nSRST	Input/Output	(可选项) System Reset，与目标板上的系统复位信号相连。可以直接对目标系统复位，同时可以检测目标系统的复位情况。为了防止误触发，应在目标端加上适当的上拉电阻。
16	GND	--	接地
17	NC		保留
18	GND	--	接地
19	NC	--	保留
20	GND	--	接地

ITM - instrumentation trace macrocell

General description

The ITM is an application-driven trace source that supports printf style debugging
to trace Operating System (OS) and application events, and emits diagnostic system information.
The ITM emits trace information as packets which can be generated as:
● Software trace. Software can write directly to the ITM stimulus registers to emit packets.
● Hardware trace. The DWT generates these packets, and the ITM emits them.
● Time stamping. Timestamps are emitted relative to packets.
The ITM contains a 21-bit counter to generate the timestamp.
The Cortex™-M3 clock or the bit clock rate of the Serial Wire Viewer (SWV) output clocks the counter.

The packets emitted by the ITM are output to the TPIU (Trace Port Interface Unit).
The formatter of the TPIU adds some extra packets (refer to TPIU) and
then output the complete packets sequence to the debugger host.

The bit TRCEN of the Debug Exception and Monitor Control Register must be enabled before you program or use the ITM.

ETM - embedded trace macrocell

General description

The ETM enables the reconstruction of program execution.
Data are traced using the Data Watchpoint and Trace (DWT) component or
the Instruction Trace Macrocell (ITM) whereas instructions are traced
using the Embedded Trace Macrocell (ETM).

The ETM transmits information as packets and is triggered by embedded resources.
These resources must be programmed independently and the trigger source
is selected using the Trigger Event Register (0xE0041008).
An event could be a simple event (address match from an address comparator)
or a logic equation between 2 events.

The trigger source is one of the fourth comparators of the DWT module,
The following events can be monitored:

● Clock cycle matching
● Data address matching

For more informations on the trigger resources refer to Section 31.13: DWT (data watchpoint trigger).

The packets transmitted by the ETM are output to the TPIU (Trace Port Interface Unit).
The formatter of the TPIU adds some extra packets
and then outputs the complete packet sequence to the debugger host.

DWT - data watchpoint and trace

The DWT unit consists of four comparators. They are configurable as:

● a hardware watchpoint or
● a trigger to an ETM or
● a PC sampler or
● a data address sampler

The DWT also provides some means to give some profiling informations.
For this, some counters are accessible to give the number of:

● Clock cycle
● Folded instructions
● Load store unit (LSU) operations
● Sleep cycles
● CPI (clock per instructions)
● Interrupt overhead

TPIU (trace port interface unit)

The TPIU acts as a bridge between the on-chip trace data from the ITM and the ETM.
The output data stream encapsulates the trace source ID,
that is then captured by a trace port analyzer (TPA).
The core embeds a simple TPIU, especially designed for low-cost debug
(consisting of a special version of the CoreSight TPIU).

Serial Wire Debug (SWD)

SWD为pin有限的应用提供了一个调试的端口，主要是面向small package的微控制器，
也面向复杂的ASICs—pin数量有限并且成本控制的应用。
SWD使用一个时钟+双向数据管脚来取代5-pin的JTAG端口，提供了所有的通用的JTAG调试和测试功能，
并且增加了：在没有中断内核以及没有增加额外的代码的情况下，对系统内存的实时访问。
SWD使用了一个ARM标准的双向有线协议，这已在ARM Debug Interface v5中定义。
SWD在调试器和目标系统之间用一种高效标准的方式互相传送数据。它是ARM-based设备的标准接口。
SWD提供了一种简单可靠的从JTAG的移植，只需在TMS和TCK管脚上覆盖SWDIO和SWCLK信号，
允许双模的设备，这可以提供另外的JTAG信号。在SWD模式中，这些额外的JTAG管脚可被用来作其他的用途。

SWD和所有的ARM核以及所有的使用JTAG的核兼容，并且在Cortex核以及CoreSight调试架构中提供了对调试寄存器的访问。

Serial Wire Output(SWO)

支持Serial Wire Output(SWO)意思是指支持从core引出一个pin的输出信号。
这个功能目前只在Cortex-M3上测试通过。  它这意味着更快的传输速度，并且不会中断程序的执行。

Serial Wire Viewer(SWV)

Serial Wire Output(SWO) 和 Instrumentation Trace Macrocell(ITM) 可以用来共同构成一个Serial Wire Viewer(SWV)。
SWV提供了一种低成本的从MCU获得信息的方法。
SWO可用两种格式输出调试信息，但在一个时间只能输出一种格式的调试信息。

这两种编码方式是UART和曼彻斯特编码。

SWV使用SWO pin来传输不同的信息包。在Cortex-M3 Core中，有三种源信息可以通过此pin来传输：

对应用驱动跟踪源（支持printf格式的调试）的ITM，它支持32路通道，使得其可以用于例如real-time kernal信息的其他用途。

对实时变量的监测以及PC-sampling的Data Watchpoint和Trace(DWT)，这可以用来定时的输出PC或者CPU内部不同计数器的值，
可以用来从目标板获得分析信息。

Timestamping。和包有关的Timestamping。

The Serial Wire Debug mode is an alternative to the standard JTAG interface.

SWD uses 2-pins to provide the same debug functionality as JTAG with no performance penalty,
and introduces data trace capabilities with the Serial Wire Viewer (SWV).

The SWD interface pins can be overlayed with the JTAG signals, allowing the standard target connectors to be used.

• TCLK - SWCLK (Serial Wire Clock)
• TMS - SWDIO (Serial Wire debug Data Input/Output)
• TDO - SWO (output pin for Serial Wire Viewer)

 

STM32 - SWJ debug port ( SWD and JTAG)

The STM32 core integrates the Serial Wire / JTAG Debug Port (SWJ-DP).
It is an ARM standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and
a SWDP (2-pin) interface.

The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHPAP port.
The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP port.

In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP.

The asynchronous TRACE output (TRACESWO) is multiplexed with TDO.
This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP.

SWD and JTAG selection mechanism

SWJ-DP enables one of the following modes to be selected:

• JTAG protocol

• Serial Wire Debug protocol

• Dormant.

When in Dormant mode, the TMS, TDI, and TDO signals can be used for other purposes,
enabling alternative debug protocols to be used by other devices connected to the same pins.

The switcher defaults to JTAG operation on power-on reset, therefore
the JTAG protocol can be used from reset without sending a selection sequence.

The SWJ-DP contains a mode status output, JTAGNSW,
that is HIGH when the SWJ-DP is in JTAG mode and LOW when in SWD or Dormant mode.
This signal can be used to:

• disable other TAP controllers when the SWJ-DP is in SWD or Dormant mode,
  for example by disabling TCK or forcing TMS HIGH

• multiplex the Serial Wire output, TRACESWO,
  onto another pin such as TDO when not in JTAG mode.

Another status output, JTAGTOP, indicates the state of the JTAG-DP TAP controller. These states are:

• Test-Logic-Reset

• Run-Test/Idle

• Select-DR-Scan

• Select-IR-Scan.

This signal can be used with JTAGNSW to control multiplexers so that,
for example, TDO and TDI can be reused as General Purpose Input/Output (GPIO) signals
when the device is not in JTAG mode, or during cycles when these signals are not in use by the JTAG-DP TAP controller.

By default, the JTAG-Debug Port is active.

If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG sequence on TMS/TCK
(respectively mapped to SWDIO and SWCLK) which disables the JTAG-DP and enables the SW-DP.
This way it is possible to activate the SWDP using only the SWCLK and SWDIO pins.

This sequence is:

1. Send more than 50 TCK cycles with TMS (SWDIO) =1
2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted first)
3. Send more than 50 TCK cycles with TMS (SWDIO) =1

STM32 - JTAG TAP connections