• xilinx 自定义IP 生成vhdl文件 探索


    // 大结构就两个entity my_axi_ip is  ,architecture IMP of my_axi_ip is
    //
    //architecture IMP of my_axi_ip is 里面有两个元件调用一个是  自定义ip,另一个是axi_lite_ipif_v1_01_a.axi_lite_ipif;
     调用这两个元件,然后在结构中把这两个连起来,看上去像是   xilinx 提供了一个很全面的ip框架,然后你自己把你定义的ip的对应端口跟框架端口连接起来
    这个样子,添加的对外输出的端口则要在 声明实体,声明元件,元件例化的时候手动添加进去。

    刚接触xilinx和VHDL,这是个自我探索,有错误还希望大家提出,谢谢~

    1
    S_AXI_ACLK : in std_logic; 2 S_AXI_ARESETN : in std_logic; 3 S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 4 S_AXI_AWVALID : in std_logic; 5 S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 6 S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); 7 S_AXI_WVALID : in std_logic; 8 S_AXI_BREADY : in std_logic; 9 S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 10 S_AXI_ARVALID : in std_logic; 11 S_AXI_RREADY : in std_logic; 12 S_AXI_ARREADY : out std_logic; 13 S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 14 S_AXI_RRESP : out std_logic_vector(1 downto 0); 15 S_AXI_RVALID : out std_logic; 16 S_AXI_WREADY : out std_logic; 17 S_AXI_BRESP : out std_logic_vector(1 downto 0); 18 S_AXI_BVALID : out std_logic; 19 S_AXI_AWREADY : out std_logic

    上面是entity my_axi_ip is,这个包括所有axi总线接口了

    architecture IMP of my_axi_ip is
    
      constant USER_SLV_DWIDTH                : integer              := C_S_AXI_DATA_WIDTH;
    
      constant IPIF_SLV_DWIDTH                : integer              := C_S_AXI_DATA_WIDTH;
    
      constant ZERO_ADDR_PAD                  : std_logic_vector(0 to 31) := (others => '0');
      constant USER_SLV_BASEADDR              : std_logic_vector     := C_BASEADDR;
      constant USER_SLV_HIGHADDR              : std_logic_vector     := C_HIGHADDR;
    
      constant IPIF_ARD_ADDR_RANGE_ARRAY      : SLV64_ARRAY_TYPE     := 
        (
          ZERO_ADDR_PAD & USER_SLV_BASEADDR,  -- user logic slave space base address
          ZERO_ADDR_PAD & USER_SLV_HIGHADDR   -- user logic slave space high address
        );
    
      constant USER_SLV_NUM_REG               : integer              := 1;
      constant USER_NUM_REG                   : integer              := USER_SLV_NUM_REG;
      constant TOTAL_IPIF_CE                  : integer              := USER_NUM_REG;
    
      constant IPIF_ARD_NUM_CE_ARRAY          : INTEGER_ARRAY_TYPE   := 
        (
          0  => (USER_SLV_NUM_REG)            -- number of ce for user logic slave space
        );

    自定义ip结构

     1 component user_logic is
     2     generic
     3     (
     4       -- ADD USER GENERICS BELOW THIS LINE ---------------
     5       --USER generics added here
     6       -- ADD USER GENERICS ABOVE THIS LINE ---------------
     7 
     8       -- DO NOT EDIT BELOW THIS LINE ---------------------
     9       -- Bus protocol parameters, do not add to or delete
    10       C_NUM_REG                      : integer              := 1;
    11       C_SLV_DWIDTH                   : integer              := 32
    12       -- DO NOT EDIT ABOVE THIS LINE ---------------------
    13     );
    14     port
    15     (
    16       -- ADD USER PORTS BELOW THIS LINE ------------------
    17       LED                                : out std_logic_vector(7 downto 0);
    18       -- ADD USER PORTS ABOVE THIS LINE ------------------
    19 
    20       -- DO NOT EDIT BELOW THIS LINE ---------------------
    21       -- Bus protocol ports, do not add to or delete
    22       Bus2IP_Clk                     : in  std_logic;
    23       Bus2IP_Resetn                  : in  std_logic;
    24       Bus2IP_Data                    : in  std_logic_vector(C_SLV_DWIDTH-1 downto 0);
    25       Bus2IP_BE                      : in  std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
    26       Bus2IP_RdCE                    : in  std_logic_vector(C_NUM_REG-1 downto 0);
    27       Bus2IP_WrCE                    : in  std_logic_vector(C_NUM_REG-1 downto 0);
    28       IP2Bus_Data                    : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
    29       IP2Bus_RdAck                   : out std_logic;
    30       IP2Bus_WrAck                   : out std_logic;
    31       IP2Bus_Error                   : out std_logic
    32       -- DO NOT EDIT ABOVE THIS LINE ---------------------
    33     );
    34   end component user_logic;
    35 
    36 begin
    37 
    38   ------------------------------------------
    39   -- instantiate axi_lite_ipif
    40   ------------------------------------------
    41   AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
    42     generic map
    43     (
    44       C_S_AXI_DATA_WIDTH             => IPIF_SLV_DWIDTH,
    45       C_S_AXI_ADDR_WIDTH             => C_S_AXI_ADDR_WIDTH,
    46       C_S_AXI_MIN_SIZE               => C_S_AXI_MIN_SIZE,
    47       C_USE_WSTRB                    => C_USE_WSTRB,
    48       C_DPHASE_TIMEOUT               => C_DPHASE_TIMEOUT,
    49       C_ARD_ADDR_RANGE_ARRAY         => IPIF_ARD_ADDR_RANGE_ARRAY,
    50       C_ARD_NUM_CE_ARRAY             => IPIF_ARD_NUM_CE_ARRAY,
    51       C_FAMILY                       => C_FAMILY
    52     )
    53     port map
    54     (
    55       S_AXI_ACLK                     => S_AXI_ACLK,
    56       S_AXI_ARESETN                  => S_AXI_ARESETN,
    57       S_AXI_AWADDR                   => S_AXI_AWADDR,
    58       S_AXI_AWVALID                  => S_AXI_AWVALID,
    59       S_AXI_WDATA                    => S_AXI_WDATA,
    60       S_AXI_WSTRB                    => S_AXI_WSTRB,
    61       S_AXI_WVALID                   => S_AXI_WVALID,
    62       S_AXI_BREADY                   => S_AXI_BREADY,
    63       S_AXI_ARADDR                   => S_AXI_ARADDR,
    64       S_AXI_ARVALID                  => S_AXI_ARVALID,
    65       S_AXI_RREADY                   => S_AXI_RREADY,
    66       S_AXI_ARREADY                  => S_AXI_ARREADY,
    67       S_AXI_RDATA                    => S_AXI_RDATA,
    68       S_AXI_RRESP                    => S_AXI_RRESP,
    69       S_AXI_RVALID                   => S_AXI_RVALID,
    70       S_AXI_WREADY                   => S_AXI_WREADY,
    71       S_AXI_BRESP                    => S_AXI_BRESP,
    72       S_AXI_BVALID                   => S_AXI_BVALID,
    73       S_AXI_AWREADY                  => S_AXI_AWREADY,
    74       Bus2IP_Clk                     => ipif_Bus2IP_Clk,
    75       Bus2IP_Resetn                  => ipif_Bus2IP_Resetn,
    76       Bus2IP_Addr                    => ipif_Bus2IP_Addr,
    77       Bus2IP_RNW                     => ipif_Bus2IP_RNW,
    78       Bus2IP_BE                      => ipif_Bus2IP_BE,
    79       Bus2IP_CS                      => ipif_Bus2IP_CS,
    80       Bus2IP_RdCE                    => ipif_Bus2IP_RdCE,
    81       Bus2IP_WrCE                    => ipif_Bus2IP_WrCE,
    82       Bus2IP_Data                    => ipif_Bus2IP_Data,
    83       IP2Bus_WrAck                   => ipif_IP2Bus_WrAck,
    84       IP2Bus_RdAck                   => ipif_IP2Bus_RdAck,
    85       IP2Bus_Error                   => ipif_IP2Bus_Error,
    86       IP2Bus_Data                    => ipif_IP2Bus_Data
    87     );
    //
     1   USER_LOGIC_I : component user_logic
     2     generic map
     3     (
     4       -- MAP USER GENERICS BELOW THIS LINE ---------------
     5       --USER generics mapped here
     6       -- MAP USER GENERICS ABOVE THIS LINE ---------------
     7 
     8       C_NUM_REG                      => USER_NUM_REG,
     9       C_SLV_DWIDTH                   => USER_SLV_DWIDTH
    10     )
    11     port map
    12     (
    13       -- MAP USER PORTS BELOW THIS LINE ------------------
    14       LED                            => LED,
    15       -- MAP USER PORTS ABOVE THIS LINE ------------------
    16 
    17       Bus2IP_Clk                     => ipif_Bus2IP_Clk,
    18       Bus2IP_Resetn                  => ipif_Bus2IP_Resetn,
    19       Bus2IP_Data                    => ipif_Bus2IP_Data,
    20       Bus2IP_BE                      => ipif_Bus2IP_BE,
    21       Bus2IP_RdCE                    => user_Bus2IP_RdCE,
    22       Bus2IP_WrCE                    => user_Bus2IP_WrCE,
    23       IP2Bus_Data                    => user_IP2Bus_Data,
    24       IP2Bus_RdAck                   => user_IP2Bus_RdAck,
    25       IP2Bus_WrAck                   => user_IP2Bus_WrAck,
    26       IP2Bus_Error                   => user_IP2Bus_Error
    27     );
    28 
    29   ------------------------------------------
    30   -- connect internal signals
    31   ------------------------------------------
    32   ipif_IP2Bus_Data <= user_IP2Bus_Data;
    33   ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
    34   ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
    35   ipif_IP2Bus_Error <= user_IP2Bus_Error;
    36 
    37   user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
    38   user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
    39 
    40 end IMP;
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  • 原文地址:https://www.cnblogs.com/puck/p/2968829.html
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