一、第一阶段，无修改
二、第二阶段
u-boot-1.3.4lib_armoard.c
1.增加头文件
2.增加版本号
3.start_armboot中初始化部分
板级初始化部分init_sequence->board_init
3.1创建新单板资源头文件includeasm-armarch-at91sam9at91sam9m10g45ek.h(地址与中断号)
文件书写思路：
1.参考同系列芯片的at91sam9263.h文件
2.外设标识符
3.用户外围物理基地址
4.系统外设物理基地址（基于系统控制寄存器）
5.内部存储基地址
参照图表：
附上源代码:
1 #ifndef AT91SAM9G45_H 2 #define AT91SAM9G45_H 3 4 /* 5 * Peripheral identifiers/interrupts. 6 */ 7 #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 8 #define AT91_ID_SYS 1 /* System Controller Interrupt */ 9 #define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ 10 #define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ 11 #define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ 12 #define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ 13 #define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ 14 #define AT91SAM9G45_ID_US0 7 /* USART 0 */ 15 #define AT91SAM9G45_ID_US1 8 /* USART 1 */ 16 #define AT91SAM9G45_ID_US2 9 /* USART 2 */ 17 #define AT91SAM9G45_ID_US3 10 /* USART 3 */ 18 #define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ 19 #define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ 20 #define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ 21 #define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ 22 #define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ 23 #define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ 24 #define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ 25 #define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ 26 #define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ 27 #define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ 28 #define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ 29 #define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ 30 #define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ 31 #define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ 32 #define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ 33 #define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ 34 #define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ 35 #define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ 36 #define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ 37 #define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ 38 #define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ 39 40 /* 41 * User Peripheral physical base addresses. 42 */ 43 #define AT91SAM9G45_BASE_UDPHS 0xfff78000 44 #define AT91SAM9G45_BASE_TC0 0xfff7c000 45 #define AT91SAM9G45_BASE_TC1 0xfff7c040 46 #define AT91SAM9G45_BASE_TC2 0xfff7c080 47 #define AT91SAM9G45_BASE_MCI0 0xfff80000 48 #define AT91SAM9G45_BASE_TWI0 0xfff84000 49 #define AT91SAM9G45_BASE_TWI1 0xfff88000 50 #define AT91SAM9G45_BASE_US0 0xfff8c000 51 #define AT91SAM9G45_BASE_US1 0xfff90000 52 #define AT91SAM9G45_BASE_US2 0xfff94000 53 #define AT91SAM9G45_BASE_US3 0xfff98000 54 #define AT91SAM9G45_BASE_SSC0 0xfff9c000 55 #define AT91SAM9G45_BASE_SSC1 0xfffa0000 56 #define AT91SAM9G45_BASE_SPI0 0xfffa4000 57 #define AT91SAM9G45_BASE_SPI1 0xfffa8000 58 #define AT91SAM9G45_BASE_AC97C 0xfffac000 59 #define AT91SAM9G45_BASE_TSC 0xfffb0000 60 #define AT91SAM9G45_BASE_ISI 0xfffb4000 61 #define AT91SAM9G45_BASE_PWMC 0xfffb8000 62 #define AT91SAM9G45_BASE_EMAC 0xfffbc000 63 #define AT91SAM9G45_BASE_AES 0xfffc0000 64 #define AT91SAM9G45_BASE_TDES 0xfffc4000 65 #define AT91SAM9G45_BASE_SHA 0xfffc8000 66 #define AT91SAM9G45_BASE_TRNG 0xfffcc000 67 #define AT91SAM9G45_BASE_MCI1 0xfffd0000 68 #define AT91SAM9G45_BASE_TC3 0xfffd4000 69 #define AT91SAM9G45_BASE_TC4 0xfffd4040 70 #define AT91SAM9G45_BASE_TC5 0xfffd4080 71 #define AT91_BASE_SYS 0xffffe200 72 73 /* 74 * System Peripherals (offset from AT91_BASE_SYS) 75 */ 76 #define AT91_ECC (0xffffe200 - AT91_BASE_SYS) 77 #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) 78 #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 79 #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) 80 #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 81 #define AT91_DMA (0xffffec00 - AT91_BASE_SYS) 82 #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) 83 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 84 #define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) 85 #define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) 86 #define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) 87 #define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) 88 #define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) 89 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 90 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 91 #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 92 #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) 93 #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) 94 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 95 #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 96 #define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) 97 98 #define AT91_USART0 AT91SAM9G45_BASE_US0 99 #define AT91_USART1 AT91SAM9G45_BASE_US1 100 #define AT91_USART2 AT91SAM9G45_BASE_US2 101 #define AT91_USART3 AT91SAM9G45_BASE_US3 102 103 /* 104 * Internal Memory. 105 */ 106 #define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 107 #define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ 108 109 #define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ 110 #define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ 111 112 #define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ 113 #define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ 114 #define AT91SAM9G45_HCI_BASE 0x00700000 /* USB Host controller (OHCI) */ 115 #define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ 116 #define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ 117 118 #define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 119 120 121 #endif
3.2 创建单板总线矩阵头文件includeasm-armarch-at91sam9at91sam9g45_matrix.h（地址）
文件书写思路：
1.参考同系列芯片的at91sam9263_matrix.h文件
2.寄存器映射表
参照图表：
附上源代码：
1 #ifndef AT91SAM9G45_MATRIX_H 2 #define AT91SAM9G45_MATRIX_H 3 4 #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 5 #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 6 #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 7 #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 8 #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 9 #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 10 #define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ 11 #define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ 12 #define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ 13 #define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ 14 #define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ 15 #define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ 16 #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 17 #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 18 #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 19 #define AT91_MATRIX_ULBT_FOUR (2 << 0) 20 #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 21 #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 22 #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) 23 #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) 24 #define AT91_MATRIX_ULBT_128 (7 << 0) 25 26 #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 27 #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 28 #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 29 #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 30 #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 31 #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 32 #define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ 33 #define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ 34 #define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 35 #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 36 #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 37 #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 38 #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 39 #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ 40 41 #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 42 #define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ 43 #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 44 #define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ 45 #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 46 #define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ 47 #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 48 #define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ 49 #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 50 #define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ 51 #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 52 #define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ 53 #define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ 54 #define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ 55 #define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ 56 #define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ 57 #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 58 #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 59 #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 60 #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ 61 #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ 62 #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ 63 #define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ 64 #define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ 65 #define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ 66 #define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ 67 #define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ 68 #define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ 69 70 #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 71 #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 72 #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 73 #define AT91_MATRIX_RCB2 (1 << 2) 74 #define AT91_MATRIX_RCB3 (1 << 3) 75 #define AT91_MATRIX_RCB4 (1 << 4) 76 #define AT91_MATRIX_RCB5 (1 << 5) 77 #define AT91_MATRIX_RCB6 (1 << 6) 78 #define AT91_MATRIX_RCB7 (1 << 7) 79 #define AT91_MATRIX_RCB8 (1 << 8) 80 #define AT91_MATRIX_RCB9 (1 << 9) 81 #define AT91_MATRIX_RCB10 (1 << 10) 82 #define AT91_MATRIX_RCB11 (1 << 11) 83 84 #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ 85 #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 86 #define AT91_MATRIX_ITCM_0 (0 << 0) 87 #define AT91_MATRIX_ITCM_32 (6 << 0) 88 #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ 89 #define AT91_MATRIX_DTCM_0 (0 << 4) 90 #define AT91_MATRIX_DTCM_32 (6 << 4) 91 #define AT91_MATRIX_DTCM_64 (7 << 4) 92 #define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ 93 #define AT91_MATRIX_TCM_NO_WS (0x0 << 11) 94 #define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) 95 96 #define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ 97 #define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ 98 #define AT91C_VDEC_SEL_OFF (0 << 0) 99 #define AT91C_VDEC_SEL_ON (1 << 0) 100 101 #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ 102 #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ 103 #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 104 #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) 105 #define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ 106 #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) 107 #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 108 #define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ 109 #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) 110 #define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) 111 #define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ 112 #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) 113 #define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) 114 #define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ 115 #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) 116 #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) 117 #define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ 118 #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) 119 #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) 120 #define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ 121 #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) 122 #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) 123 #define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ 124 #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) 125 #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) 126 127 #define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ 128 #define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ 129 #define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) 130 #define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) 131 #define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ 132 133 #define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ 134 #define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ 135 #define AT91_MATRIX_WPSR_NO_WPV (0 << 0) 136 #define AT91_MATRIX_WPSR_WPV (1 << 0) 137 #define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ 138 139 #endif
3.3 创建单板初始化文件u-boot-1.3.4/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
文件书写思路：
1)参考同系列芯片的at91sam9263ek.c文件
2)初始化队列中board_init()
2.1)控制台初始化
2.2)机器ID初始化
2.3)启动参数存储地址初始化
2.4)串口硬件初始化
2.4.1)设置复用GPIO口为A设备
2.4.2)写寄存器，使能时钟开启(参数是外设标识符)
2.5)nandflash硬件初始化
2.5.1) 读取片选寄存器
2.5.2) 设置EBI片选3分配给静态存储控制器
2.5.3) 设置静态存储控制器
2.5.4) 外设时钟开启寄存器，并行IO控制器C
2.5.5) C8初始化为输入
2.5.6) C14初始化为输出
2.6)spi硬件初始化
2.6.1) 设置B3为复用GPIO口B设备，用作NPCS0
2.6.2) 设置B0为复用GPIO口B设备，用作MISO0
2.6.3) 设置B1为复用GPIO口B设备，用作MOSI0
2.6.4) 设置B2为复用GPIO口B设备，用作SPCK0
2.6.5) 写寄存器，使能时钟开启(参数是外设标识符SPI0)
2.7)macb硬件初始化
2.7.1) 禁止上拉A15 A12 A13
2.7.2) 读取复位寄存模式寄存器
2.7.3) 设置复位寄存器周期，允许复位
2.7.4) 设置外部复位
2.7.5) 等待硬件复位结束
2.7.6) 设置允许复位
2.7.7) 使能上拉A15 A12 A13
2.7.8) 复用IO A10-19 为A设备 功能:ETXCK_EREFCK、ERXDV、ERX0、ERX1、ERXER、ETXEN、ETX0、ETX1、EMDIO、EMDC
2.7.9) 复用IO A6-9 A27-30 为B设备 功能：ECRS、ECOL、ERX2、ERX3、ERXCK、ETX2、ETX3、ETXER
2.7.10) D5引脚复位
2.8)lcd硬件初始化
2.8.1) 复用IO E0 E4-30 为A设备 功能:LCDDPWR、LCDHSYNC、LCDDOTCK、LCDDEN、LCDD0-23
2.8.1) 外设时钟开启寄存器，LCD
3) 初始化队列中dram_init()
3.1) 初始化RAM起始地址0x70000000
3.2) 初始化RAM大小0x08000000
附上源码:
1 #include <common.h> 2 #include <asm/sizes.h> 3 #include <asm/arch/at91sam9g45.h> 4 #include <asm/arch/at91sam9g45_matrix.h> 5 #include <asm/arch/at91sam9_smc.h> 6 #include <asm/arch/at91_pmc.h> 7 #include <asm/arch/at91_rstc.h> 8 #include <asm/arch/gpio.h> 9 #include <asm/arch/io.h> 10 #include <lcd.h> 11 //#include <asm_blackfin/delay.h> //have udelay() 12 #include <atmel_lcdc.h> 13 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 14 #include <net.h> 15 #endif 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 /* ------------------------------------------------------------------------- */ 20 /* 21 * Miscelaneous platform dependent initialisations 22 */ 23 24 static void at91samm10g45ek_serial_hw_init(void) 25 { 26 #ifdef CONFIG_USART0 27 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */ 28 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */ 29 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0); 30 #endif 31 32 #ifdef CONFIG_USART1 33 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */ 34 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */ 35 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1); 36 #endif 37 38 #ifdef CONFIG_USART2 39 at91_set_A_periph(AT91_PIN_PD6, 1); /* TXD2 */ 40 at91_set_A_periph(AT91_PIN_PD7, 0); /* RXD2 */ 41 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2); 42 #endif 43 44 #ifdef CONFIG_USART3 /* DBGU */ 45 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */ 46 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */ 47 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); 48 #endif 49 } 50 51 #ifdef CONFIG_CMD_NAND 52 static void at91samm10g45ek_nand_hw_init(void) 53 { 54 unsigned long csa; 55 56 /* Enable CS3 */ 57 //EBI 片选 3 分配给静态存储控制器 58 csa = at91_sys_read(AT91_MATRIX_EBICSA); 59 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); 60 61 /* Configure SMC CS3 for NAND/SmartMedia */ 62 //NWE 建立时长=(128 X NWE_SETUP[5] + NWE_SETUP[4:0])时钟周期 63 //NCS 建立时长=（128 X NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]）时钟周期 64 //NRD 建立时长=(128 X NRD_SETUP[5] + NRD_SETUP[4:0])时钟周期 65 //NCS 建立时长=（128 X NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]）时钟周期 66 at91_sys_write(AT91_SMC_SETUP(3), 67 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | 68 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); 69 //NWE 脉宽=（256 X NWE_PULSE[6] + NWE_PULSE[5:0]）时钟周期 70 //NCS 脉宽=（256 X NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]）时钟周期 71 //NRD 脉宽=（256 X NRD_PULSE[6] + NRD_PULSE[5:0]）时钟周期 72 //NCS 脉宽=（256 X NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]）时钟周期 73 at91_sys_write(AT91_SMC_PULSE(3), 74 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) | 75 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2)); 76 //写周期长度=（NWE_CYCLE[8:7] X 256 + NWE_CYCLE[6:0]）时钟周期 77 //读周期长度=（NRD_CYCLE[8:7] X 256 + NRD_CYCLE[6:0]）时钟周期 78 at91_sys_write(AT91_SMC_CYCLE(3), 79 AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4)); 80 //读操作是由 NRD 信号来控制的。 81 //写操作是由 NWE 信号控制的 82 //NWAIT 是用来扩展当前的读或写信号的，它只在读和写控制信号的脉宽才会被考虑。如果NWAIT 启用了，在读和写控制信号中必须设置至少一个周期。 83 //数据总线宽度8-位总线 84 //数据浮动时间: 外部设备在读控制信号上升沿后释放数据的整数个周期时间 85 at91_sys_write(AT91_SMC_MODE(3), 86 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 87 AT91_SMC_EXNWMODE_DISABLE | 88 #ifdef CFG_NAND_DBW_16 89 AT91_SMC_DBW_16 | 90 #else /* CFG_NAND_DBW_8 */ 91 AT91_SMC_DBW_8 | 92 #endif 93 AT91_SMC_TDF_(3)); 94 //外设时钟开启寄存器 并行IO控制器C 95 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC); 96 97 /* Configure RDY/BSY */ 98 //输入初始化 99 at91_set_gpio_input(AT91_PIN_PC8, 1); 100 101 /* Enable NandFlash */ 102 //输出初始化 103 at91_set_gpio_output(AT91_PIN_PC14, 1); 104 } 105 #endif 106 107 #ifdef CONFIG_HAS_DATAFLASH 108 static void at91samm10g45ek_spi_hw_init(void) 109 { 110 at91_set_B_periph(AT91_PIN_PB3, 0); /* SPI0_NPCS0 */ 111 112 at91_set_B_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */ 113 at91_set_B_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */ 114 at91_set_B_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */ 115 116 /* Enable clock */ 117 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0); 118 } 119 #endif 120 121 #ifdef CONFIG_MACB 122 /***********md9161 reset test****************/ 123 //D5脚复位网卡 124 static void macb_reset(void) 125 { 126 int i; 127 128 at91_set_gpio_output(AT91_PIN_PD5,0); 129 130 //puts("macb_reset... "); 131 for(i=0;i<500000;i++) 132 { 133 ; 134 } 135 136 // udelay(200*1000); 137 138 at91_set_gpio_output(AT91_PIN_PD5,1); 139 140 } 141 142 /***************************************/ 143 static void at91samm10g45ek_macb_hw_init(void) 144 { 145 unsigned long rstc; 146 147 // macb_reset();//reset dm9161 148 149 /* Enable clock */ 150 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC); 151 152 /* 153 * Disable pull-up on: 154 * RXDV (PA15) => PHY normal mode (not Test mode) 155 * ERX0 (PA12) => PHY ADDR0 156 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 157 * 158 * PHY has internal pull-down 159 */ 160 161 /*AC97*/ 162 //at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */ 163 //at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */ 164 //禁止上拉 A15 A12 A13 165 writel(pin_to_mask(AT91_PIN_PA15) | 166 pin_to_mask(AT91_PIN_PA12) | 167 pin_to_mask(AT91_PIN_PA13), 168 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); 169 //读取复位寄存模式寄存器 170 rstc = at91_sys_read(AT91_RSTC_MR); 171 172 /* Need to reset PHY -> 500ms reset */ 173 //KEY:应该设为 0xA5。如果设成其他值，会中止写操作 174 //外部复位的时长，这个值为 2 （ERSTL+1） 个低速时钟周期。所以这个值的范围 175 //检测到 NRST (复位)引脚一个 low 电平，触发一个用户复位 176 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 177 (AT91_RSTC_ERSTL & (0x0D << 8)) | 178 AT91_RSTC_URSTEN); 179 // 复位控制器控制寄存器 180 //外部复位:如果 KEY 正确，插入 NRST (复位)引脚 181 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); 182 183 //复位控制器状态寄存器 184 //读取以主控制器时钟频率（MCK）锁存 NRST (复位)引脚的电平 目的:等待硬件复位结束 185 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); 186 187 /* Restore NRST value */ 188 //如果检测到 NRST (复位)引脚一个 low 电平，触发一个用户复位 189 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 190 (rstc) | 191 AT91_RSTC_URSTEN); 192 //使能上拉 A15 A12 A13 193 /* Re-enable pull-up */ 194 writel(pin_to_mask(AT91_PIN_PA15) | 195 pin_to_mask(AT91_PIN_PA12) | 196 pin_to_mask(AT91_PIN_PA13), 197 pin_to_controller(AT91_PIN_PA0) + PIO_PUER); 198 199 //at91_set_gpio_output(AT91_PIN_PA30,1); //pull up PA30 200 //复用IO A10-19 为A设备 201 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ 202 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */ 203 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ 204 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ 205 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */ 206 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */ 207 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */ 208 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */ 209 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ 210 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ 211 212 #ifndef CONFIG_RMII 213 //复用IO A6-9 A27-30 为B设备 214 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ 215 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ 216 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ 217 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */ 218 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */ 219 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */ 220 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */ 221 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */ 222 #endif 223 macb_reset();//reset dm9161 224 //printf("macb_reset... "); 225 } 226 #endif 227 228 #ifdef CONFIG_LCD 229 vidinfo_t panel_info = { 230 vl_col: 480, 231 vl_row: 272, 232 vl_clk: 125000, 233 vl_sync: ATMEL_LCDC_INVLINE_NORMAL | 234 ATMEL_LCDC_INVFRAME_NORMAL, 235 vl_bpix: 3, 236 vl_tft: 1, 237 vl_hsync_len: 41, 238 vl_left_margin: 2, 239 vl_right_margin:2, 240 vl_vsync_len: 1, 241 vl_upper_margin:2, 242 vl_lower_margin:2, 243 mmio: AT91SAM9G45_LCDC_BASE, 244 }; 245 246 void lcd_enable(void) 247 { 248 at91_set_gpio_value(AT91_PIN_PE6, 1); /* power up */ 249 } 250 251 void lcd_disable(void) 252 { 253 at91_set_gpio_value(AT91_PIN_PE6, 0); /* power down */ 254 } 255 256 static void at91samm10g45ek_lcd_hw_init(void) 257 { 258 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ 259 260 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ 261 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ 262 263 at91_set_gpio_input(AT91_PIN_PE6, 0); /* LCDDEN */ 264 265 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ 266 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ 267 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ 268 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ 269 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ 270 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ 271 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ 272 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ 273 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ 274 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ 275 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ 276 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ 277 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ 278 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ 279 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ 280 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ 281 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ 282 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ 283 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ 284 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ 285 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ 286 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ 287 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ 288 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ 289 290 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC); 291 292 gd->fb_base = AT91SAM9G45_SRAM_BASE; 293 } 294 #endif 295 296 #if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) 297 extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); 298 299 int board_eth_init(bd_t *bis) 300 { 301 macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00); 302 } 303 #endif 304 305 int board_init(void) 306 { 307 /* Enable Ctrlc */ 308 console_init_f(); 309 /* arch number of AT91SAM9M10G45EK-Board */ 310 #ifdef CONFIG_AT91SAM9M10G45EK 311 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK; 312 #elif defined CONFIG_AT91SAM9G45EKES 313 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; 314 #elif defined CONFIG_AT91SAM9M10EKES 315 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10EKES; 316 #endif 317 /* adress of boot parameters */ 318 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;//启动参数地址，DDR内存位置 319 320 at91samm10g45ek_serial_hw_init(); 321 #ifdef CONFIG_CMD_NAND 322 at91samm10g45ek_nand_hw_init(); 323 #endif 324 #ifdef CONFIG_HAS_DATAFLASH 325 at91samm10g45ek_spi_hw_init(); 326 #endif 327 #ifdef CONFIG_MACB 328 at91samm10g45ek_macb_hw_init(); 329 #endif 330 331 #ifdef CONFIG_LCD 332 at91samm10g45ek_lcd_hw_init(); 333 #endif 334 return 0; 335 } 336 337 int dram_init(void) 338 { 339 gd->bd->bi_dram[0].start = PHYS_SDRAM; 340 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 341 printf(" ++++++++++++++++++++++++++++++++++++++++++++ "); 342 return 0; 343 } 344 345 #ifdef CONFIG_RESET_PHY_R 346 void reset_phy(void) 347 { 348 #ifdef CONFIG_MACB 349 /* 350 * Initialize ethernet HW addr prior to starting Linux, 351 * needed for nfsroot 352 */ 353 //puts("reset_phy "); 354 eth_init(gd->bd); 355 #endif 356 } 357 #endif
3.4 board.c中NAND初始化
1) driversmtd and and.c标准函数nand_init->nand_init_chip->board_nand_init
2) 增加nand文件boardatmelat91sam9m10g45ek and.c
2.1) board_nand_init初始化函数
2.1.1) 初始化eccmode 软件ECC对应字节数
2.1.2) 初始化options 总线宽度
2.1.3) 初始化hwcontrol 硬件控制函数
2.1.4) 初始化dev_ready 准备就绪函数
2.1.5) 初始化chip_delay 芯片时序延迟参数
2.2) hwcontrol 硬件控制函数
2.3) dev_ready 准备就绪函数
3.5 board.c中NOR初始化 使用的AT45DB161 2M NOR Flash
1) driversmtddataflash.c标准函数AT91F_DataflashInit->AT91F_SpiInit->AT91F_DataflashProbe 得到ID=c2 即AT45DB161
2) 依据ID初始化页数量、页大小、页偏移、基地址
