LVTTL
The LVTTL standard is a single-ended, general-purpose standard for 3.3-V applications. The maximum recommended input voltage for Mercury devices is 4.1 V, which exceeds the 3.9-V requirement of this specification. This standard requires the output buffer to drive to 2.4 V (minimum V OH = 2.4 V) but does not require the use of input reference voltages or termination. The LVTTL interface is defined by JEDEC Standard JESD 8-A, Interface Standard for Nominal 3.0 V/3.3 V Supply Digital Integrated Circuits.
LVCMOS
LVCMOS is a single-ended general-purpose standard used for 3.3-V applications. The input buffer requirements are the same as the LVTTL requirements, and the output buffer is required to drive to the rail (minimum V OH = V CCIO – 0.2 V). This standard requires a 3.3-V I/O supply voltage (V CCIO ), but not the use of input reference voltages or termination. The LVCMOS standard is defined in JEDEC Standard JESD 8-A, Interface Standard for Nominal 3.0 V/3.3 V Supply Digital Integrated Circuits.
2.5 V
The 2.5-V standard is similar to LVCMOS but is used for 2.5-V power supply levels. Mercury devices meet the normal range of this specification. This standard requires a 2.5-V V CCIO , but not the use of input reference voltages or termination. The 2.5-V I/O standard is documented by JEDEC Standard JESD 8-5, 2.5 V ±0.2 V (Normal Range) and 1.7 V to 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit.
1.8 V
The 1.8-V I/O standard is similar to LVCMOS but is used for 1.8-V power supply levels and reduced input and output thresholds. Mercury devices meet the normal range of this specification. This standard requires a 1.8-V V CCIO , but not the use of input reference voltages or termination. The 1.8-V I/O standard is documented by JEDEC Standard JESD 8-7, 1.8 V ±0.15 V (Normal Range) and 1.2 V to 1.95 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit.
3.3-V PCI
Mercury devices are compliant with PCI Local Bus Specification, Revision 2.2 for 3.3-V operation. At 3.3 V, the PCI standard supports up to 64-bit bus width operation at 33 or 66 MHz. This standard uses LVTTL-type input and output buffers and requires a 3.3-V V CCIO , but not the use of input reference voltages or termination.
PCI-X
An enhanced version of the PCI specification that can support higher average bandwidth, PCI-X has more stringent requirements than PCI. PCI-X provides backward compatibility by allowing devices to operate at conventional PCI frequencies (33 MHz and 66 MHz).
LVDS
The LVDS I/O standard is used for very high-performance, low-power- consumption data transfer. Two key industry standards define LVDS: IEEE 1596.3 SCI-LVDS and ANSI/TIA/EIA-644. Both standards have similar key features, but the IEEE standard supports a maximum data transfer of 250 megabits per second (Mbps). Mercury devices are designed to meet the ANSI/TIA/EIA-644 requirements at up to 840 Mbps using source syncronous mode, and up to 1.25 Gbps in CDR mode. The LVDS termination resistor between thestandard requires a 3.3-V V CCIO and a 100- two traces at the input buffer. No input reference voltage is required.
LVPECL
The LVPECL standard is used in video graphic, telecommunications, and data communication designs. It is also used for clock distribution.LVPECL is a differential I/O standard that is similar to LVDS, but with a different common mode and differential voltage. The LVPECL standard termination resistor between the two tracesrequires a 3.3-V V CCIO and a 100- at the input buffer. No input reference voltage is required.
PCML
PCML is a differential standard used for high-speed interfacing. PCML requires a termination resistor between the two traces at the3.3-V V CCIO and a 100- resistor to V TT ,input buffer. In addition, each input trace requires a 50- resistor to V TT . No input referenceand each output trace requires a 100- voltage is required.
GTL+
The GTL+ standard is a high-speed bus standard first used by Intel Corporation for interfacing with the Pentium Pro processor. GTL+ is a voltage-referenced standard requiring a 1.0-V input V REF and a 1.5-V V TT . Because GTL+ is an open-drain standard, it does not require a particular V CCIO supply voltage. GTL+ is often used for processor interfacing or communication across a backplane.
HSTL Class I, II, III & IV
The HSTL standard is a 1.5-V output buffer supply voltage-based interface standard for digital integrated circuits. HSTL is a voltage-referenced standard requiring a 0.75-V V REF , a 1.5-V V CCIO , and a 0.75-V V TT . HSTL class III and IV require a 0.9-V V REF , a 1.5-V V CCIO , and a 1.5-V V TT .The HSTL standard is specified by JEDEC Standard JESD 8-6, High-Speed Transceiver Logic (HSTL).
SSTL-2 Class I & II
The SSTL-2 standard is a voltage-referenced standard requiring a 1.125-V V REF , a 2.5-V V CCIO , and a 1.125-V V TT . SSTL-2 is used for high-speed SDRAM interfaces. The SSTL-2 I/O standard is specified by JEDEC Standard JESD 8-9, Stub-Series Terminated Logic for 2.5 Volts (SSTL-2).
SSTL-3 Class I & II
The SSTL-3 standard is a voltage-referenced standard requiring a 1.5-V V REF , a 3.3-V V CCIO , and a 1.5-V V TT . SSTL-3 is used for high-speed SDRAM interfaces. The SSTL-3 I/O standard is specified by JEDEC Standard JESD 8-8, Stub-Series Terminated Logic for 3.3 Volts (SSTL-3).
AGP
Mercury devices support the AGP interface is a voltage-referenced standard requiring a 1.32-Vmodes. AGP and in both
CTT
CTT is a voltage-referenced standard requiring a 1.5-V V REF , a 3.3-V V CCIO , and a 1.5-V V TT . CTT drivers, when not terminated, are compatible with the AC and DC specifications for LVCMOS and LVTTL. The CTT standard is specified by JEDEC Standard JESD 8-4, Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface Standard for Digital
Integrated Circuits.