作者信息
作者：彭东林
QQ: 405728433
平台介绍
开发环境：win7 64位 + VMware11 + Ubuntu14.04 64位
开发板：tiny4412ADK + S700 + 4GB eMMC + 1G DDR3
工具链：友善之臂提供的 arm-linux- (gcc version 4.5.1)
要移植的u-boot版本：u-boot-2015-10
参考u-boot版本：友善之臂提供的 u-boot-2010-12
移植
有了上一篇的基础，下面开始移植。
我采用的u-boot版本是u-boot-2015-10，其中已经有了对exynos4412比较好的支持。
在board/samsung下有很多可以供我们参考的：origen、odroid、trats、trats2等等。经过对比发现，只有origen支持的配置支持spl，适合tiny4412，其他三个不适合tiny4412，以odroid为例，这个配置最后之编译出一个镜像u-boot-dtb.bin，没有spl，结合exynos4412的启动，即便把u-boot-dtb.bin的前14KB强制截出来作为BL2，在BL2代码中的board_init_f中调用的一些函数的相对地址（相对于spl起始地址，即0x02023400）已经超过14KB，甚至超过16KB，我们知道，BL2是在iRAM中运行的，并且地址空间最多16KB，所以会导致问题。
- 仿照origen在u-boot中添加tiny4412的目录和配置文件
1、创建tiny4412板级目录
cp board/samsung/origen board/samsung/tiny4412 –raf
mv board/samsung/tiny4412/origen.c board/samsung/tiny4412/tiny4412.c
mv board/samsung/tiny4412/tools/mkorigenspl.c board/samsung/tiny4412/tools/mktiny4412spl.c
2、增加配置文件
cp include/configs/origen.h include/configs/tiny4412.h
cp configs/origen_defconfig configs/tiny4412_defconfig
cp arch/arm/dts/exynos4412-odroid.dts arch/arm/dts/exynos4412-tiny4412.dts
3、修改配置文件
3.1 修改arch/arm/dts/Makefile，用于编译设备树
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 65b4230..26dddff 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -5,7 +5,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb
exynos4210-universal_c210.dtb
exynos4210-trats.dtb
exynos4412-trats2.dtb
- exynos4412-odroid.dtb
+ exynos4412-odroid.dtb
+ exynos4412-tiny4412.dtb
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb
exynos5250-snow.dtb
3.2 修改arch/arm/include/asm/mach-types.h，增加tiny4412的machine ID
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index d51be0b..1784a6b 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1062,6 +1062,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_MONCH 3453
#define MACH_TYPE_CURACAO 3454
#define MACH_TYPE_ORIGEN 3455
+#define MACH_TYPE_TINY4412 4608
#define MACH_TYPE_EPC10 3456
#define MACH_TYPE_SGH_I740 3457
#define MACH_TYPE_TUNA 3458
3.3 修改arch/arm/mach-exynos/Kconfig，在执行make menuconfig的时候会看到
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index a6a7597..1845a78 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -19,6 +19,10 @@ config TARGET_ORIGEN
bool "Exynos4412 Origen board"
select SUPPORT_SPL
+config TARGET_TINY4412
+ bool "Exynos4412 Tiny4412 board"
+ select SUPPORT_SPL
+
config TARGET_TRATS2
bool "Exynos4412 Trat2 board"
@@ -76,6 +80,7 @@ source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
source "board/samsung/universal_c210/Kconfig"
source "board/samsung/origen/Kconfig"
+source "board/samsung/tiny4412/Kconfig"
source "board/samsung/trats2/Kconfig"
source "board/samsung/odroid/Kconfig"
source "board/samsung/arndale/Kconfig"
3.4 修改 board/samsung/tiny4412/Kconfig
diff --git a/board/samsung/tiny4412/Kconfig b/board/samsung/tiny4412/Kconfig
new file mode 100644
index 0000000..06a7905
--- /dev/null
+++ b/board/samsung/tiny4412/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TINY4412
+
+config SYS_BOARD
+ default "tiny4412"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "tiny4412"
+
+endif
3.5 修改board/samsung/tiny4412/Makefile
--- /dev/null
+++ b/board/samsung/tiny4412/Makefile
@@ -0,0 +1,22 @@
+#
+# Copyright (C) 2011 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+
+hostprogs-y := tools/mktiny4412spl
+always := $(hostprogs-y)
+
+# omit -O2 option to suppress
+# warning: dereferencing type-punned pointer will break strict-aliasing rules
+#
+# TODO:
+# Fix the root cause in tools/mkorigenspl.c and delete the following work-around
+$(obj)/tools/mktiny4412spl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
+else
+obj-y += tiny4412.o
+endif
3.6 修改arch/arm/dts/exynos4412-tiny4412.dts，使用uart0作为终端
diff --git a/arch/arm/dts/exynos4412-tiny4412.dts b/arch/arm/dts/exynos4412-tiny4412.dts
new file mode 100644
index 0000000..d2122f3
--- /dev/null
+++ b/arch/arm/dts/exynos4412-tiny4412.dts
@@ -0,0 +1,29 @@
+/*
+ * Tiny4412 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "exynos4412.dtsi"
+
+/ {
+ model = "Tiny4412 based on Exynos4412";
+ compatible = "samsung,tiny4412", "samsung,exynos4412";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ aliases {
+ serial0 = "/serial@13800000";
+ console = "/serial@13800000";
+ };
+
+ serial0:serial@13810000 {
+ status = "okay";
+ };
+};
3.7 修改 arch/arm/mach-exynos/Makefile，在tiny4412.h中会定义CONFIG_TINY4412这个宏
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8542f89..1b13070 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,7 +12,9 @@ obj-$(CONFIG_EXYNOS5420) += sec_boot.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
-obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
+ifneq (,$(filter y, $(CONFIG_EXYNOS4210) $(CONFIG_TINY4412)))
+obj-y += dmc_init_exynos4.o clock_init_exynos4.o
+endif
obj-y += spl_boot.o
obj-y += lowlevel_init.o
endif
3.8 修改 arch/arm/mach-exynos/clock_init_exynos4.c，时钟初始化
diff --git a/arch/arm/mach-exynos/clock_init_exynos4.c b/arch/arm/mach-exynos/clock_init_exynos4.c
index 584e4ba..e07e32e 100644
--- a/arch/arm/mach-exynos/clock_init_exynos4.c
+++ b/arch/arm/mach-exynos/clock_init_exynos4.c
@@ -30,7 +30,11 @@
#include <;asm/arch/clk.h>
#include <;asm/arch/clock.h>
#include "common_setup.h"
+#ifdef CONFIG_TINY4412
+#include "tiny4412_setup.h"
+#else
#include "exynos4_setup.h"
+#endif
/*
* system_clock_init: Initialize core clock and bus clock.
@@ -38,6 +42,269 @@
*/
void system_clock_init(void)
{
+#ifdef CONFIG_TINY4412
+ unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
+ struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
+ samsung_get_base_clock();
+
+ /*
+ * CMU_CPU clocks src to MPLL
+ * Bit values: 0 ; 1
+ * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
+ * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
+ * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
+ * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
+ */
+ clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
+ MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
+ set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
+ MUX_MPLL_USER_SEL_C(1);
+
+ clrsetbits_le32(&;clk->src_cpu, clr_src_cpu, set);
+
+ /* Wait for mux change */
+ while (readl(&;clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
+ continue;
+
+ /* Set APLL to 1400MHz */
+ clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
+ set = SDIV(0x0) | PDIV(0x3) | MDIV(0xAF) | FSEL(1);
+
+ clrsetbits_le32(&;clk->apll_con0, clr_pll_con0, set);
+
+ /* Wait for PLL to be locked */
+ while (!(readl(&;clk->apll_con0) & PLL_LOCKED_BIT))
+ continue;
+
+ /* Set CMU_CPU clocks src to APLL */
+ set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
+ MUX_MPLL_USER_SEL_C(1);
+ clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
+
+ /* Wait for mux change */
+ while (readl(&;clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
+ continue;
+
+ set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
+ PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
+ APLL_RATIO(0) | CORE2_RATIO(0);
+ /*
+ * Set dividers for MOUTcore = 1400 MHz
+ * coreout = MOUT / (ratio + 1) = 1400 MHz (0)
+ * corem0 = armclk / (ratio + 1) = 466 MHz (2)
+ * corem1 = armclk / (ratio + 1) = 233 MHz (5)
+ * periph = armclk / (ratio + 1) = 1400 MHz (0)
+ * atbout = MOUT / (ratio + 1) = 280 MHz (4)
+ * pclkdbgout = atbout / (ratio + 1) = 140 MHz (1)
+ * sclkapll = MOUTapll / (ratio + 1) = 1400 MHz (0)
+ * core2out = core_out / (ratio + 1) = 1400 MHz (0) (armclk)
+ */
+ clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
+ PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
+ APLL_RATIO(7) | CORE2_RATIO(7);
+
+ clrsetbits_le32(&;clk->div_cpu0, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&;clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
+ continue;
+
+ /*
+ * For MOUThpm = 1400 MHz (MOUTapll)
+ * doutcopy = MOUThpm / (ratio + 1) = 280 (4)
+ * sclkhpm = doutcopy / (ratio + 1) = 280 (4)
+ * cores_out = armclk / (ratio + 1) = 280 (4)
+ */
+ clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
+ set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
+
+ clrsetbits_le32(&;clk->div_cpu1, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&;clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
+ continue;
+
+ /*
+ * Set CMU_DMC clocks src to APLL
+ * Bit values: 0 ; 1
+ * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
+ * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
+ * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
+ * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
+ */
+ clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
+ MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
+ MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
+ MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
+ set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
+ MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
+ MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
+
+ clrsetbits_le32(&;clk->src_dmc, clr_src_dmc, set);
+
+ /* Wait for mux change */
+ while (readl(&;clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
+ continue;
+
+ /* Set MPLL to 800MHz */
+ set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
+
+ clrsetbits_le32(&;clk->mpll_con0, clr_pll_con0, set);
+
+ /* Wait for PLL to be locked */
+ while (!(readl(&;clk->mpll_con0) & PLL_LOCKED_BIT))
+ continue;
+
+ /* Switch back CMU_DMC mux */
+ set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
+ MUX_MPLL_SEL(1) | MUX_PWI_SEL(6) | MUX_G2D_ACP0_SEL(0) |
+ MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
+
+ clrsetbits_le32(&;clk->src_dmc, clr_src_dmc, set);
+
+ /* Wait for mux change */
+ while (readl(&;clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
+ continue;
+
+ /* CLK_DIV_DMC0 */
+ clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
+ DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
+ /*
+ * For:
+ * MOUTdmc = 800 MHz
+ * MOUTdphy = 800 MHz
+ *
+ * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
+ * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
+ * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
+ * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
+ * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
+ * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
+ */
+ set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
+ DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
+
+ clrsetbits_le32(&;clk->div_dmc0, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&;clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
+ continue;
+
+ /* CLK_DIV_DMC1 */
+ clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
+ C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
+ /*
+ * For:
+ * MOUTg2d = 800 MHz
+ * MOUTc2c = 800 Mhz
+ * MOUTpwi = 800 MHz
+ *
+ * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
+ * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
+ * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
+ * sclk_pwi = MOUTpwi / (ratio + 1) = 100 (7)
+ */
+ set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(7) |
+ C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
+
+ clrsetbits_le32(&;clk->div_dmc1, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&;clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
+ continue;
+
+ /* CLK_SRC_PERIL0 */
+ clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
+ UART3_SEL(15) | UART4_SEL(15);
+ /*
+ * Set CLK_SRC_PERIL0 clocks src to MPLL
+ * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
+ * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
+ * 8(SCLK_VPLL)
+ *
+ * Set all to SCLK_MPLL_USER_T
+ */
+ set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
+ UART4_SEL(6);
+
+ clrsetbits_le32(&;clk->src_peril0, clr, set);
+
+ /* CLK_DIV_PERIL0 */
+ clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
+ UART3_RATIO(15) | UART4_RATIO(15);
+ /*
+ * For MOUTuart0-4: 800MHz
+ *
+ * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
+ */
+ set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
+ UART3_RATIO(7) | UART4_RATIO(7);
+
+ clrsetbits_le32(&;clk->div_peril0, clr, set);
+
+ while (readl(&;clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
+ continue;
+
+ /* CLK_DIV_FSYS1 */
+ clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
+ MMC1_PRE_RATIO(255);
+ /*
+ * For MOUTmmc0-3 = 800 MHz (MPLL)
+ *
+ * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
+ * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
+ * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
+ * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
+ */
+ set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
+ MMC1_PRE_RATIO(1);
+
+ clrsetbits_le32(&;clk->div_fsys1, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&;clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
+ continue;
+
+ /* CLK_DIV_FSYS2 */
+ clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
+ MMC3_PRE_RATIO(255);
+ /*
+ * For MOUTmmc0-3 = 800 MHz (MPLL)
+ *
+ * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
+ * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
+ * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
+ * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
+ */
+ set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
+ MMC3_PRE_RATIO(1);
+
+ clrsetbits_le32(&;clk->div_fsys2, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&;clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
+ continue;
+
+ /* CLK_DIV_FSYS3 */
+ clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
+ /*
+ * For MOUTmmc4 = 800 MHz (MPLL)
+ *
+ * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
+ * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
+ */
+ set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
+
+ clrsetbits_le32(&;clk->div_fsys3, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&;clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
+ continue;
+#else
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
@@ -91,4 +358,5 @@ void system_clock_init(void)
writel(VPLL_CON0_VAL, &clk->vpll_con0);
sdelay(0x30000);
+#endif
}
增加头文件arch/arm/mach-exynos/tiny4412_setup.h
diff --git a/arch/arm/mach-exynos/tiny4412_setup.h b/arch/arm/mach-exynos/tiny4412_setup.h
new file mode 100644
index 0000000..8c14e09
--- /dev/null
+++ b/arch/arm/mach-exynos/tiny4412_setup.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <;p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TINY4412_SETUP__
+#define __TINY4412_SETUP__
+
+/* A/M PLL_CON0 */
+#define SDIV(x) ((x) &; 0x7)
+#define PDIV(x) (((x) &; 0x3f) << 8)
+#define MDIV(x) (((x) &; 0x3ff) << 16)
+#define FSEL(x) (((x) &; 0x1) << 27)
+#define PLL_LOCKED_BIT (0x1 <;< 29)
+#define PLL_ENABLE(x) (((x) &; 0x1) << 31)
+
+/* CLK_SRC_CPU */
+#define MUX_APLL_SEL(x) ((x) &; 0x1)
+#define MUX_CORE_SEL(x) (((x) &; 0x1) << 16)
+#define MUX_HPM_SEL(x) (((x) &; 0x1) << 20)
+#define MUX_MPLL_USER_SEL_C(x) (((x) &; 0x1) << 24)
+
+#define MUX_STAT_CHANGING 0x100
+
+/* CLK_MUX_STAT_CPU */
+#define APLL_SEL(x) ((x) &; 0x7)
+#define CORE_SEL(x) (((x) &; 0x7) << 16)
+#define HPM_SEL(x) (((x) &; 0x7) << 20)
+#define MPLL_USER_SEL_C(x) (((x) &; 0x7) << 24)
+#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) |
+ CORE_SEL(MUX_STAT_CHANGING) |
+ HPM_SEL(MUX_STAT_CHANGING) |
+ MPLL_USER_SEL_C(MUX_STAT_CHANGING))
+
+/* CLK_DIV_CPU0 */
+#define CORE_RATIO(x) ((x) &; 0x7)
+#define COREM0_RATIO(x) (((x) &; 0x7) << 4)
+#define COREM1_RATIO(x) (((x) &; 0x7) << 8)
+#define PERIPH_RATIO(x) (((x) &; 0x7) << 12)
+#define ATB_RATIO(x) (((x) &; 0x7) << 16)
+#define PCLK_DBG_RATIO(x) (((x) &; 0x7) << 20)
+#define APLL_RATIO(x) (((x) &; 0x7) << 24)
+#define CORE2_RATIO(x) (((x) &; 0x7) << 28)
+
+/* CLK_DIV_STAT_CPU0 */
+#define DIV_CORE(x) ((x) &; 0x1)
+#define DIV_COREM0(x) (((x) &; 0x1) << 4)
+#define DIV_COREM1(x) (((x) &; 0x1) << 8)
+#define DIV_PERIPH(x) (((x) &; 0x1) << 12)
+#define DIV_ATB(x) (((x) &; 0x1) << 16)
+#define DIV_PCLK_DBG(x) (((x) &; 0x1) << 20)
+#define DIV_APLL(x) (((x) &; 0x1) << 24)
+#define DIV_CORE2(x) (((x) &; 0x1) << 28)
+
+#define DIV_STAT_CHANGING 0x1
+#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) |
+ DIV_COREM0(DIV_STAT_CHANGING) |
+ DIV_COREM1(DIV_STAT_CHANGING) |
+ DIV_PERIPH(DIV_STAT_CHANGING) |
+ DIV_ATB(DIV_STAT_CHANGING) |
+ DIV_PCLK_DBG(DIV_STAT_CHANGING) |
+ DIV_APLL(DIV_STAT_CHANGING) |
+ DIV_CORE2(DIV_STAT_CHANGING))
+
+/* CLK_DIV_CPU1 */
+#define COPY_RATIO(x) ((x) &; 0x7)
+#define HPM_RATIO(x) (((x) &; 0x7) << 4)
+#define CORES_RATIO(x) (((x) &; 0x7) << 8)
+
+/* CLK_DIV_STAT_CPU1 */
+#define DIV_COPY(x) ((x) &; 0x7)
+#define DIV_HPM(x) (((x) &; 0x1) << 4)
+#define DIV_CORES(x) (((x) &; 0x1) << 8)
+
+#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) |
+ DIV_HPM(DIV_STAT_CHANGING) |
+ DIV_CORES(DIV_STAT_CHANGING))
+
+/* CLK_SRC_DMC */
+#define MUX_C2C_SEL(x) ((x) &; 0x1)
+#define MUX_DMC_BUS_SEL(x) (((x) &; 0x1) << 4)
+#define MUX_DPHY_SEL(x) (((x) &; 0x1) << 8)
+#define MUX_MPLL_SEL(x) (((x) &; 0x1) << 12)
+#define MUX_PWI_SEL(x) (((x) &; 0xf) << 16)
+#define MUX_G2D_ACP0_SEL(x) (((x) &; 0x1) << 20)
+#define MUX_G2D_ACP1_SEL(x) (((x) &; 0x1) << 24)
+#define MUX_G2D_ACP_SEL(x) (((x) &; 0x1) << 28)
+
+/* CLK_MUX_STAT_DMC */
+#define C2C_SEL(x) (((x)) &; 0x7)
+#define DMC_BUS_SEL(x) (((x) &; 0x7) << 4)
+#define DPHY_SEL(x) (((x) &; 0x7) << 8)
+#define MPLL_SEL(x) (((x) &; 0x7) << 12)
+/* #define PWI_SEL(x) (((x) &; 0xf) << 16) - Reserved */
+#define G2D_ACP0_SEL(x) (((x) &; 0x7) << 20)
+#define G2D_ACP1_SEL(x) (((x) &; 0x7) << 24)
+#define G2D_ACP_SEL(x) (((x) &; 0x7) << 28)
+
+#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) |
+ DMC_BUS_SEL(MUX_STAT_CHANGING) |
+ DPHY_SEL(MUX_STAT_CHANGING) |
+ MPLL_SEL(MUX_STAT_CHANGING) |
+ G2D_ACP0_SEL(MUX_STAT_CHANGING) |
+ G2D_ACP1_SEL(MUX_STAT_CHANGING) |
+ G2D_ACP_SEL(MUX_STAT_CHANGING))
+
+/* CLK_DIV_DMC0 */
+#define ACP_RATIO(x) ((x) &; 0x7)
+#define ACP_PCLK_RATIO(x) (((x) &; 0x7) << 4)
+#define DPHY_RATIO(x) (((x) &; 0x7) << 8)
+#define DMC_RATIO(x) (((x) &; 0x7) << 12)
+#define DMCD_RATIO(x) (((x) &; 0x7) << 16)
+#define DMCP_RATIO(x) (((x) &; 0x7) << 20)
+
+/* CLK_DIV_STAT_DMC0 */
+#define DIV_ACP(x) ((x) &; 0x1)
+#define DIV_ACP_PCLK(x) (((x) &; 0x1) << 4)
+#define DIV_DPHY(x) (((x) &; 0x1) << 8)
+#define DIV_DMC(x) (((x) &; 0x1) << 12)
+#define DIV_DMCD(x) (((x) &; 0x1) << 16)
+#define DIV_DMCP(x) (((x) &; 0x1) << 20)
+
+#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) |
+ DIV_ACP_PCLK(DIV_STAT_CHANGING) |
+ DIV_DPHY(DIV_STAT_CHANGING) |
+ DIV_DMC(DIV_STAT_CHANGING) |
+ DIV_DMCD(DIV_STAT_CHANGING) |
+ DIV_DMCP(DIV_STAT_CHANGING))
+
+/* CLK_DIV_DMC1 */
+#define G2D_ACP_RATIO(x) ((x) &; 0xf)
+#define C2C_RATIO(x) (((x) &; 0x7) << 4)
+#define PWI_RATIO(x) (((x) &; 0xf) << 8)
+#define C2C_ACLK_RATIO(x) (((x) &; 0x7) << 12)
+#define DVSEM_RATIO(x) (((x) &; 0x7f) << 16)
+#define DPM_RATIO(x) (((x) &; 0x7f) << 24)
+
+/* CLK_DIV_STAT_DMC1 */
+#define DIV_G2D_ACP(x) ((x) &; 0x1)
+#define DIV_C2C(x) (((x) &; 0x1) << 4)
+#define DIV_PWI(x) (((x) &; 0x1) << 8)
+#define DIV_C2C_ACLK(x) (((x) &; 0x1) << 12)
+#define DIV_DVSEM(x) (((x) &; 0x1) << 16)
+#define DIV_DPM(x) (((x) &; 0x1) << 24)
+
+#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) |
+ DIV_C2C(DIV_STAT_CHANGING) |
+ DIV_PWI(DIV_STAT_CHANGING) |
+ DIV_C2C_ACLK(DIV_STAT_CHANGING) |
+ DIV_DVSEM(DIV_STAT_CHANGING) |
+ DIV_DPM(DIV_STAT_CHANGING))
+
+/* Set CLK_SRC_PERIL0 */
+#define UART4_SEL(x) (((x) &; 0xf) << 16)
+#define UART3_SEL(x) (((x) &; 0xf) << 12)
+#define UART2_SEL(x) (((x) &; 0xf) << 8)
+#define UART1_SEL(x) (((x) &; 0xf) << 4)
+#define UART0_SEL(x) ((x) &; 0xf)
+
+/* Set CLK_DIV_PERIL0 */
+#define UART4_RATIO(x) (((x) &; 0xf) << 16)
+#define UART3_RATIO(x) (((x) &; 0xf) << 12)
+#define UART2_RATIO(x) (((x) &; 0xf) << 8)
+#define UART1_RATIO(x) (((x) &; 0xf) << 4)
+#define UART0_RATIO(x) ((x) &; 0xf)
+
+/* Set CLK_DIV_STAT_PERIL0 */
+#define DIV_UART4(x) (((x) &; 0x1) << 16)
+#define DIV_UART3(x) (((x) &; 0x1) << 12)
+#define DIV_UART2(x) (((x) &; 0x1) << 8)
+#define DIV_UART1(x) (((x) &; 0x1) << 4)
+#define DIV_UART0(x) ((x) &; 0x1)
+
+#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) |
+ DIV_UART3(DIV_STAT_CHANGING) |
+ DIV_UART2(DIV_STAT_CHANGING) |
+ DIV_UART1(DIV_STAT_CHANGING) |
+ DIV_UART0(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS1 */
+#define MMC0_RATIO(x) ((x) &; 0xf)
+#define MMC0_PRE_RATIO(x) (((x) &; 0xff) << 8)
+#define MMC1_RATIO(x) (((x) &; 0xf) << 16)
+#define MMC1_PRE_RATIO(x) (((x) &; 0xff) << 24)
+
+/* CLK_DIV_STAT_FSYS1 */
+#define DIV_MMC0(x) ((x) &; 1)
+#define DIV_MMC0_PRE(x) (((x) &; 1) << 8)
+#define DIV_MMC1(x) (((x) &; 1) << 16)
+#define DIV_MMC1_PRE(x) (((x) &; 1) << 24)
+
+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) |
+ DIV_MMC0_PRE(DIV_STAT_CHANGING) |
+ DIV_MMC1(DIV_STAT_CHANGING) |
+ DIV_MMC1_PRE(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO(x) ((x) &; 0xf)
+#define MMC2_PRE_RATIO(x) (((x) &; 0xff) << 8)
+#define MMC3_RATIO(x) (((x) &; 0xf) << 16)
+#define MMC3_PRE_RATIO(x) (((x) &; 0xff) << 24)
+
+/* CLK_DIV_STAT_FSYS2 */
+#define DIV_MMC2(x) ((x) &; 0x1)
+#define DIV_MMC2_PRE(x) (((x) &; 0x1) << 8)
+#define DIV_MMC3(x) (((x) &; 0x1) << 16)
+#define DIV_MMC3_PRE(x) (((x) &; 0x1) << 24)
+
+#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) |
+ DIV_MMC2_PRE(DIV_STAT_CHANGING) |
+ DIV_MMC3(DIV_STAT_CHANGING) |
+ DIV_MMC3_PRE(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS3 */
+#define MMC4_RATIO(x) ((x) &; 0x7)
+#define MMC4_PRE_RATIO(x) (((x) &; 0xff) << 8)
+
+/* CLK_DIV_STAT_FSYS3 */
+#define DIV_MMC4(x) ((x) &; 0x1)
+#define DIV_MMC4_PRE(x) (((x) &; 0x1) << 8)
+
+#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) |
+ DIV_MMC4_PRE(DIV_STAT_CHANGING))
+
+#endif /*__ODROIDU3_SETUP__ */
3.9 修改arch/arm/mach-exynos/dmc_init_exynos4.c，内存控制器初始化
diff --git a/arch/arm/mach-exynos/dmc_init_exynos4.c b/arch/arm/mach-exynos/dmc_init_exynos4.c
index ecddc72..4ddb782 100644
--- a/arch/arm/mach-exynos/dmc_init_exynos4.c
+++ b/arch/arm/mach-exynos/dmc_init_exynos4.c
@@ -28,6 +28,28 @@
#include "common_setup.h"
#include "exynos4_setup.h"
+#ifdef CONFIG_TINY4412
+struct mem_timings mem = {
+ .direct_cmd_msr = {
+ DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4
+ },
+ .timingref = 0x000000BB,
+ .timingrow = 0x4046654f,
+ .timingdata = 0x46400506,
+ .timingpower = 0x52000A3C,
+ .zqcontrol = 0xE3854C03,
+ .control0 = 0x71101008,
+ .control1 = 0xe0000086,
+ .control2 = 0x00000000,
+ .concontrol = 0x0FFF301A,
+ .prechconfig = 0xff000000,
+ .memcontrol = 0x00312640,
+ .memconfig0 = 0x40e01323,
+ .memconfig1 = 0x60e01323,
+ .dll_resync = FORCE_DLL_RESYNC,
+ .dll_on = DLL_CONTROL_ON,
+};
+#else
struct mem_timings mem = {
.direct_cmd_msr = {
DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4
@@ -48,6 +70,8 @@ struct mem_timings mem = {
.dll_resync = FORCE_DLL_RESYNC,
.dll_on = DLL_CONTROL_ON,
};
+#endif
+
static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
{
if (ctrl_no) {
@@ -124,6 +148,10 @@ static void dmc_init(struct exynos4_dmc *dmc)
writel(mem.memconfig0, &;dmc->memconfig0);
writel(mem.memconfig1, &;dmc->memconfig1);
+#ifdef CONFIG_TINY4412
+ writel(0x8000001F, &;dmc->ivcontrol);
+#endif
+
/* Config Precharge Policy */
writel(mem.prechconfig, &;dmc->prechconfig);
/*
@@ -175,6 +203,7 @@ void mem_ctrl_init(int reset)
* 0: full_sync
*/
writel(1, ASYNC_CONFIG);
+#ifndef CONFIG_TINY4412
#ifdef CONFIG_ORIGEN
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
@@ -204,6 +233,7 @@ void mem_ctrl_init(int reset)
ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
#endif
#endif
+#endif
/* DREX0 */
dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl();
dmc_init(dmc);
3.10 修改arch/arm/mach-exynos/lowlevel_init.c，使用uart0作为调试串口
diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c
index 6c39cb2..bccb74b 100644
--- a/arch/arm/mach-exynos/lowlevel_init.c
+++ b/arch/arm/mach-exynos/lowlevel_init.c
@@ -216,8 +216,9 @@ int do_lowlevel_init(void)
if (actions &; DO_CLOCKS) {
system_clock_init();
#ifdef CONFIG_DEBUG_UART
- exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
debug_uart_init();
+ printascii("UART OK.
");
#endif
mem_ctrl_init(actions &; DO_MEM_RESET);
tzpc_init();
3.11 修改arch/arm/mach-exynos/spl_boot.c，从sdcard中拷贝u-boot到dram中，目前的移植有些问题，调用iROM提供的读取sdcard的函数，发现无法直接将u-boot从sdcard拷贝到dram中，所以我想了一个walk round的办法，首先利用iROM提供的sdcard读取函数将u-boot从sdcard拷贝到iRAM中，然后再将u-boot从iRAM中拷贝到DRAM中。
diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index c7f943e..1474b9d 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c
@@ -15,6 +15,7 @@
#include <;asm/arch/power.h>
#include <;asm/arch/spl.h>
#include <;asm/arch/spi.h>
+#include <;debug_uart.h>
#include "common_setup.h"
#include "clock_init.h"
@@ -185,7 +186,7 @@ void copy_uboot_to_ram(void)
{
unsigned int bootmode = BOOT_MODE_OM;
- u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
+ u32 (*copy_uboot)(u32 offset, u32 nblock, u32 dst) = NULL;
u32 offset = 0, size = 0;
#ifdef CONFIG_SPI_BOOTING
struct spl_machine_param *param = spl_get_machine_params();
@@ -213,7 +214,6 @@ void copy_uboot_to_ram(void)
if (bootmode == BOOT_MODE_OM)
bootmode = get_boot_mode();
-
switch (bootmode) {
#ifdef CONFIG_SPI_BOOTING
case BOOT_MODE_SERIAL:
@@ -222,9 +222,9 @@ void copy_uboot_to_ram(void)
break;
#endif
case BOOT_MODE_SD:
- offset = BL2_START_OFFSET;
- size = BL2_SIZE_BLOC_COUNT;
- copy_bl2 = get_irom_func(MMC_INDEX);
+ offset = UBOOT_START_OFFSET;
+ size = UBOOT_SIZE_BLOC_COUNT;
+ copy_uboot = get_irom_func(MMC_INDEX);
break;
#ifdef CONFIG_SUPPORT_EMMC_BOOT
case BOOT_MODE_EMMC:
@@ -253,9 +253,34 @@ void copy_uboot_to_ram(void)
default:
break;
}
-
- if (copy_bl2)
- copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
+#ifdef CONFIG_TINY4412
+ if (copy_uboot)
+ {
+ /*
+ * Here I use iram 0x020250000-0x020260000 (64k)
+ * as an buffer, and copy u-boot from sd card to
+ * this buffer, then copy it to dram started
+ * from 0x43e00000.
+ *
+ */
+ unsigned int i, count = 0;
+ unsigned char *buffer = (unsigned char *)0x02050000;
+ unsigned char *dst = (unsigned char *)CONFIG_SYS_TEXT_BASE;
+ unsigned int step = (0x10000 / 512);
+
+ for (count = 0; count < UBOOT_SIZE_BLOC_COUNT; count+=step) {
+ /* copy u-boot from sdcard to iram firstly. */
+ copy_uboot((u32)(UBOOT_START_OFFSET+count), (u32)step, (u32)buffer);
+ /* then copy u-boot from iram to dram. */
+ for (i=0; i<0x10000; i++) {
+ *dst++ = buffer[i];
+ }
+ }
+ }
+#else
+ if (copy_uboot)
+ copy_uboot(offset, size, CONFIG_SYS_TEXT_BASE);
+#endif
}
void memzero(void *s, size_t n)
3.12 修改common/board_f.c，调试信息，看是否运行到u-boot
diff --git a/common/board_f.c b/common/board_f.c
index 613332e..6c7f911 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -58,6 +58,7 @@
#endif
#include <;dm/root.h>
#include <;linux/compiler.h>
+#include <;debug_uart.h>
/*
* Pointer to initial global data area
@@ -977,6 +978,7 @@ void board_init_f(ulong boot_flags)
zero_global_data();
#endif
+ printascii("Uboot running. ");
gd->flags = boot_flags;
gd->have_console = 0;
3.13 修改configs/tiny4412_defconfig
diff --git a/configs/tiny4412_defconfig b/configs/tiny4412_defconfig
new file mode 100644
index 0000000..3f2642a
--- /dev/null
+++ b/configs/tiny4412_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_TINY4412=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4412-tiny4412"
+CONFIG_SPL=y
+CONFIG_SYS_PROMPT="TINY4412 # "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_OF_CONTROL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
3.14 修改drivers/serial/serial_s5p.c，配置串口的波特率、格式等信息
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 3f0b588..70a5f17 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -62,12 +62,12 @@ static const int udivslot[] = {
static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
{
/* enable FIFOs, auto clear Rx FIFO */
- writel(0x3, &;uart->ufcon);
+ writel(0x111, &;uart->ufcon);
writel(0, &;uart->umcon);
/* 8N1 */
writel(0x3, &;uart->ulcon);
/* No interrupts, no DMA, pure polling */
- writel(0x245, &;uart->ucon);
+ writel(0x3c5, &;uart->ucon);
}
static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk,
3.15 修改include/configs/tiny4412.h
这里有几点需要注意：
1、SPL的链接地址 CONFIG_SPL_TEXT_BASE，它的值是0x02023400
2、U-boot的链接地址 CONFIG_SYS_TEXT_BASE，它的值是0x43e00000
3、SD卡的布局
diff --git a/include/configs/tiny4412.h b/include/configs/tiny4412.h
new file mode 100644
index 0000000..f9a0630
--- /dev/null
+++ b/include/configs/tiny4412.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG TINY4412 (EXYNOS4412) board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_TINY4412_H
+#define __CONFIG_TINY4412_H
+
+#include <;configs/exynos4-common.h>
+
+/* High Level Configuration Options */
+#define CONFIG_TINY4412 1
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_DEBUG_UART
+#define CONFIG_DEBUG_UART_S5P
+#define CONFIG_DEBUG_UART_BASE 0x13800000 /* UART0 base address */
+#define CONFIG_DEBUG_UART_CLOCK (100000000) /* SCLK_UART0 is 100MHz */
+
+#define CONFIG_SYS_DCACHE_OFF 1
+
+/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE (256 <;< 20) /* 256 MB */
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+
+#define CONFIG_MACH_TYPE MACH_TYPE_TINY4412
+
+/* select serial console configuration */
+#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE 115200
+
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8 "
+
+#define CONFIG_SYS_MEM_TOP_HIDE (1 <;< 20) /* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
+
+#undef CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* MMC SPL */
+#define COPY_BL2_FNPTR_ADDR 0x02020030
+/* Because bl1 will copy bl2(spl) to iram address 0x02023400 */
+#define CONFIG_SPL_TEXT_BASE 0x02023400
+
+#define CONFIG_EXTRA_ENV_SETTINGS
+ "loadaddr=0x40007000 "
+ "rdaddr=0x48000000 "
+ "kerneladdr=0x40007000 "
+ "ramdiskaddr=0x48000000 "
+ "console=ttySAC2,115200n8 "
+ "mmcdev=0 "
+ "bootenv=uEnv.txt "
+ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv} "
+ "importbootenv=echo Importing environment from mmc ...; "
+ "env import -t $loadaddr $filesize "
+ "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr "
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; "
+ "source ${loadaddr} "
+#define CONFIG_BOOTCOMMAND
+ "if mmc rescan; then "
+ "echo SD/MMC found on device ${mmcdev};"
+ "if run loadbootenv; then "
+ "echo Loaded environment from ${bootenv};"
+ "run importbootenv;"
+ "fi;"
+ "if test -n $uenvcmd; then "
+ "echo Running uenvcmd ...;"
+ "run uenvcmd;"
+ "fi;"
+ "if run loadbootscript; then "
+ "run bootscript; "
+ "fi; "
+ "fi;"
+ "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
+
+#define CONFIG_IDENT_STRING " for TINY4412"
+
+#define CONFIG_CLK_1000_400_200
+
+/* MIU (Memory Interleaving Unit) */
+#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
+
+/*
+ * SD MMC layout:
+ * +------------+------------------------------------------------------------+
+ * | |
+ * | | | | | |
+ * | 512B | 8K(bl1) | 16k(bl2) | 16k(ENV) | 512k(u-boot) |
+ * | | | | | |
+ * | |
+ * +------------+------------------------------------------------------------+
+ *
+ */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE (16 <;< 10) /* 16 KB */
+#define RESERVE_BLOCK_SIZE (512)
+#define BL1_SIZE (8 <;< 10) /*16 K reserved for BL1*/
+#define BL2_SIZE (16 <;< 10) /*16 k reserved for BL2*/
+#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE + BL2_SIZE)
+
+#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define COPY_UBOOT_SIZE 0x80000
+#define UBOOT_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
+#define UBOOT_SIZE_BLOC_COUNT (COPY_UBOOT_SIZE/512)
+
+/* #define UBOOT_DEBUG_20151226 */
+
+#endif /* __CONFIG_H */
到此基本修改完毕
- 编译方法
修改Makfile，将CROSS_COMPILE设置为arm-linux-
编译 make tiny4412_defconfig && make
编译完成后会生成 u-boot-dtb.bin 和 spl/u-boot-spl-dtb.bin
- 烧写
友善之臂提供的烧写脚本，但是不能直接使用，修改做如下修改：
1、修改sd_fuse/V310-EVT1-mkbl2.c 用于生成BL2，生成的文件大小是14KB，最后4B为校验码
diff --git a/sd_fuse/V310-EVT1-mkbl2.c b/sd_fuse/V310-EVT1-mkbl2.c
new file mode 100644
index 0000000..54bb422
--- /dev/null
+++ b/sd_fuse/V310-EVT1-mkbl2.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <;stdio.h>
+#include <;string.h>
+#include <;stdlib.h>
+
+int main (int argc, char *argv[])
+{
+ FILE *fp;
+ unsigned char src;
+ char *Buf, *a;
+ int BufLen;
+ int nbytes, fileLen;
+ unsigned int checksum = 0;
+ int i;
+
+ if (argc != 4)
+ {
+ printf("Usage: mkbl1 <source file> <destination file> <size> ");
+ return -1;
+ }
+
+ BufLen = atoi(argv[3]);
+ Buf = (char *)malloc(BufLen);
+ memset(Buf, 0x00, BufLen);
+
+ fp = fopen(argv[1], "rb");
+ if( fp == NULL)
+ {
+ printf("source file open error ");
+ free(Buf);
+ return -1;
+ }
+
+ fseek(fp, 0L, SEEK_END);
+ fileLen = ftell(fp);
+ fseek(fp, 0L, SEEK_SET);
+#if 0
+ if ( BufLen > fileLen )
+ {
+ printf("Usage: unsupported size ");
+ free(Buf);
+ fclose(fp);
+ return -1;
+ }
+#endif
+ nbytes = fread(Buf, 1, fileLen, fp);
+
+ if ( nbytes != fileLen )
+ {
+ printf("source file read error ");
+ free(Buf);
+ fclose(fp);
+ return -1;
+ }
+
+ fclose(fp);
+
+ for(i = 0;i < (14 * 1024) - 4;i++)
+ {
+ checksum += (unsigned char)(Buf[i]);
+ }
+ *(unsigned int*)(Buf+i) = checksum;
+
+ fp = fopen(argv[2], "wb");
+ if (fp == NULL)
+ {
+ printf("destination file open error ");
+ free(Buf);
+ return -1;
+ }
+
+ a = Buf;
+ nbytes = fwrite( a, 1, BufLen, fp);
+
+ if ( nbytes != BufLen )
+ {
+ printf("destination file write error ");
+ free(Buf);
+ fclose(fp);
+ return -1;
+ }
+
+ free(Buf);
+ fclose(fp);
+
+ return 0;
+}
2、修改sd_fuse/tiny4412/fast_fuse.sh，用于将BL2和u-boot烧写到SD卡中
diff --git a/sd_fuse/tiny4412/fast_fuse.sh b/sd_fuse/tiny4412/fast_fuse.sh
new file mode 100755
index 0000000..18a22ca
--- /dev/null
+++ b/sd_fuse/tiny4412/fast_fuse.sh
@@ -0,0 +1,90 @@
+#
+# Copyright (C) 2011 Samsung Electronics Co., Ltd.
+# http://www.samsung.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+####################################
+
+if [ -z $1 ]
+then
+ echo "usage: ./sd_fusing.sh <SD Reader's device file>"
+ exit 0
+fi
+
+if [ -b $1 ]
+then
+ echo "$1 reader is identified."
+else
+ echo "$1 is NOT identified."
+ exit 0
+fi
+
+####################################
+#<;verify device>
+
+BDEV_NAME=`basename $1`
+BDEV_SIZE=`cat /sys/block/${BDEV_NAME}/size`
+
+if [ ${BDEV_SIZE} -le 0 ]; then
+ echo "Error: NO media found in card reader."
+ exit 1
+fi
+
+if [ ${BDEV_SIZE} -gt 32000000 ]; then
+ echo "Error: Block device size (${BDEV_SIZE}) is too large"
+ exit 1
+fi
+
+####################################
+# check files
+
+E4412_SPL=../../spl/u-boot-spl.bin
+E4412_UBOOT=../../u-boot-dtb.bin
+MKBL2=../mkbl2
+
+if [ ! -f ${E4412_SPL} ]; then
+ echo "Error: u-boot-spl.bin NOT found, please build it & try again."
+ exit -1
+fi
+
+if [ ! -f ${E4412_UBOOT} ]; then
+ echo "Error: u-boot-dtb.bin NOT found, please build it & try again."
+ exit -1
+fi
+
+if [ ! -f ${MKBL2} ]; then
+ echo "Error: can not find host tool - mkbl2, stop."
+ exit -1
+fi
+
+#<;make bl2>
+${MKBL2} ${E4412_SPL} bl2.bin 14336
+
+####################################
+# fusing images
+
+bl2_position=17
+uboot_position=81
+
+#<;BL2 fusing>
+echo "---------------------------------------"
+echo "BL2 fusing"
+dd iflag=dsync oflag=dsync if=./bl2.bin of=$1 seek=$bl2_position
+
+#<;u-boot fusing>
+echo "---------------------------------------"
+echo "u-boot fusing"
+dd iflag=dsync oflag=dsync if=${E4412_UBOOT} of=$1 seek=$uboot_position
+
+#<;flush to disk>
+sync
+
+####################################
+#<;Message Display>
+echo "---------------------------------------"
+echo "U-boot image is fused (at `date +%T`) successfully."
+echo "Eject SD card and insert it again."
+
3、修改sd_fuse/tiny4412/sd_fusing.sh，用于烧写BL1、BL2、u-boot以及tz
diff --git a/sd_fuse/tiny4412/sd_fusing.sh b/sd_fuse/tiny4412/sd_fusing.sh
new file mode 100755
index 0000000..7c72fc1
--- /dev/null
+++ b/sd_fuse/tiny4412/sd_fusing.sh
@@ -0,0 +1,102 @@
+#
+# Copyright (C) 2011 Samsung Electronics Co., Ltd.
+# http://www.samsung.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+####################################
+
+if [ -z $1 ]
+then
+ echo "usage: ./sd_fusing.sh <SD Reader's device file>"
+ exit 0
+fi
+
+if [ -b $1 ]
+then
+ echo "$1 reader is identified."
+else
+ echo "$1 is NOT identified."
+ exit 0
+fi
+
+####################################
+#<;verify device>
+
+BDEV_NAME=`basename $1`
+BDEV_SIZE=`cat /sys/block/${BDEV_NAME}/size`
+
+if [ ${BDEV_SIZE} -le 0 ]; then
+ echo "Error: NO media found in card reader."
+ exit 1
+fi
+
+if [ ${BDEV_SIZE} -gt 32000000 ]; then
+ echo "Error: Block device size (${BDEV_SIZE}) is too large"
+ exit 1
+fi
+
+####################################
+# check files
+
+E4412_SPL=../../spl/u-boot-spl.bin
+E4412_UBOOT=../../u-boot-dtb.bin
+MKBL2=../mkbl2
+
+if [ ! -f ${E4412_SPL} ]; then
+ echo "Error: u-boot-spl.bin NOT found, please build it & try again."
+ exit -1
+fi
+
+if [ ! -f ${E4412_UBOOT} ]; then
+ echo "Error: u-boot.bin NOT found, please build it & try again."
+ exit -1
+fi
+
+if [ ! -f ${MKBL2} ]; then
+ echo "Error: can not find host tool - mkbl2, stop."
+ exit -1
+fi
+
+#<;make bl2>
+${MKBL2} ${E4412_SPL} bl2.bin 14336
+
+####################################
+# fusing images
+
+signed_bl1_position=1
+bl2_position=17
+uboot_position=81
+tzsw_position=1105
+
+#<;BL1 fusing>
+echo "---------------------------------------"
+echo "BL1 fusing"
+dd iflag=dsync oflag=dsync if=./E4412_N.bl1.bin of=$1 seek=$signed_bl1_position
+
+#<;BL2 fusing>
+echo "---------------------------------------"
+echo "BL2 fusing"
+dd iflag=dsync oflag=dsync if=./bl2.bin of=$1 seek=$bl2_position
+
+#<;u-boot fusing>
+echo "---------------------------------------"
+echo "u-boot fusing"
+dd iflag=dsync oflag=dsync if=${E4412_UBOOT} of=$1 seek=$uboot_position
+
+#<;TrustZone S/W fusing>
+echo "---------------------------------------"
+echo "TrustZone S/W fusing"
+dd iflag=dsync oflag=dsync if=./E4412_tzsw.bin of=$1 seek=$tzsw_position
+
+#<;flush to disk>
+sync
+
+####################################
+#<;Message Display>
+echo "---------------------------------------"
+echo "U-boot image is fused successfully."
+echo "Eject SD card and insert it again."
+
烧写方法
第一次烧写： ./sd_fusing.sh /dev/sdf (假设sd卡被识别为sdf)
以后烧写的时候为了提高速度，可以使用 ./fast_fuse.sh /dev/sdf
- 启动
将sd卡插入tiny4412底板上的sd卡插槽，然后设置为从sd卡启动即可。log会从COM0输出，波特率115200，无奇偶校验、一位停止位、8位数据位。
完整的代码我已经上传到github上了
下载和使用方法：
1、git clone https://github.com/pengdonglin137/u-boot -b u-boot-2015-10-tiny4412
2、修改Makefile，将CROSS_COMPILE强制设置为arm-linux-
3、make tiny4412_defconfig && make
4. cd sd_fuse/tiny4412 && ./sd_fusing /dev/sdf