Verification of WISHBONE I2C Master Core(IRUN+Simvision)

一、前言

　　很久没写技术博客了，有些懈怠，生活还得继续折腾。转眼工作一年多，时间越长越发觉得自己知之甚少，当然这跟IC行业技术密集有关。用空余时间在opencores网站上下载些小的IP看看 验证下，让自己对EDA tool, design, testbench, bus protocol都能有更好的认识。这次接触的是WISHBONE I2C Master Core。仿真验证工具是IES(Irun)+Simvision。

二、IP概述

　　这一IP也是直接从Opencores网站上下载，对于FPGA平台来说是可以直接拿来用的，还带有spec 仿真脚本，真的是贴心。网络链接见参考节。

 　　对着图简单介绍下这个IP。内部有预分频寄存器、控制寄存器、状态寄存器、发送寄存器、接收寄存器还有命令寄存器。其中控制寄存器只负责使能，而命令寄存器则是I2C 协议中相关的指令操作。IP的核心逻辑在byte command controller和bit command controller两个模块中。

　　byte command controller根据命令控制寄存器的指令来将单一的命令转换为bit级别的命令，bit command controller接受bit级命令后将每一比特划分更细的时间片操作SCL和SDA产生特定的时序。比如当读取一个字节时，bit command controller接收到8个读指令，而对于每一个比特分为5个时间片IDLE A B C D。这种分层设计方式具有很高的复用性和可读性。

 三、IES(IRUN)+Simvision工具

　　IES+Simvision是Cadence公司的仿真调试工具，Simvision的code schematic wave三者建立了映射关系，调试起来效率非常高。irun指令可以直接一起完成compilation elaboration simulation三个步骤，通过脚本观察它的使用方式。

#!/bin/tcsh

set i2c      = ../../..
set bench    = $i2c/bench
set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves

irun    -64bit                                            
                                                            
    +access+rwc                                            
    +define+WAVES                                          
                                                            
    +incdir+$bench/verilog                              
    +incdir+$i2c/rtl/verilog                          
                                                            
    $i2c/rtl/verilog/i2c_master_bit_ctrl.v        
    $i2c/rtl/verilog/i2c_master_byte_ctrl.v        
    $i2c/rtl/verilog/i2c_master_top.v                
                                                            
    $bench/verilog/i2c_slave_model.v                
    $bench/verilog/wb_master_model.v                
    $bench/verilog/tst_bench_top.v

+access+rwc 设置编译结果的访问权限为读写执行

+define+WAVES 在外部添加verilog宏定义 WAVES，相当于`define WAVES

+incdir+xxx 添加路径，把design和testbench代码路径添加其中

后边直接添加需要的.v文件

　　现在来看看WAVES宏定义的作用：

　　条件编译使能dump .sh波形的代码段。具体使用方式参考文末链接。

　　./run.csh启动仿真：

 　　仿真结束后启动Simvision的GUI。

simvision -64bit WAVES/ &

 　　终于找到在公司debug的感觉了。

四、testbench

　　自带的testbench中例化了一个wb_master_model，两个DUT以及一个i2c_slave_model。作者特意例化两个I2C master意在验证I2C协议中多总线机制。我们可以从Simvision的schematic中直观地看到tb的整体结构。

 　　testbench中利用wb_master_model内部的task来实现总线读写Core寄存器，也就是充当MCU中CPU的角色。原有的testbench code存在些问题，解决后添加了测试中断信号的部分代码。源代码如下：

`include "timescale.v"
module tst_bench_top();

    //
    // wires && regs
    //
    reg  clk;
    reg  rstn;

    wire [31:0] adr;
  wire [2:0] adr_i;
    wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i;
    wire we;
    wire stb;
    wire cyc;
    wire ack;
    wire inta0,inta1;

    reg [7:0] q, qq;

    wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
    wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;

    parameter PRER_LO = 3'b000;
    parameter PRER_HI = 3'b001;
    parameter CTR     = 3'b010;
    parameter RXR     = 3'b011;
    parameter TXR     = 3'b011;
    parameter CR      = 3'b100;
    parameter SR      = 3'b100;

    parameter TXR_R   = 3'b101; // undocumented / reserved output
    parameter CR_R    = 3'b110; // undocumented / reserved output

    parameter RD      = 1'b1;
    parameter WR      = 1'b0;
    parameter SADR    = 7'b0010_000;
  parameter WAIT_TIME=50_000;

    //
    // Module body
    //

    // generate clock
    always #5 clk = ~clk;

    // hookup wishbone master model
    wb_master_model #(8, 32) u0 (
        .clk(clk),
        .rst(rstn),
        .adr(adr),
        .din(dat_i),
        .dout(dat_o),
        .cyc(cyc),
        .stb(stb),
        .we(we),
        .sel(),
        .ack(ack),
        .err(1'b0),
        .rty(1'b0)
    );

    wire stb0 = stb & ~adr[3];
    wire stb1 = stb &  adr[3];
  assign adr_i = adr[2:0];

    assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i);

    // hookup wishbone_i2c_master core
    i2c_master_top i2c_top (

        // wishbone interface
        .wb_clk_i(clk),
        .wb_rst_i(1'b0),
        .arst_i(rstn),
        .wb_adr_i(adr_i),
        .wb_dat_i(dat_o),
        .wb_dat_o(dat0_i),
        .wb_we_i(we),
        .wb_stb_i(stb0),
        .wb_cyc_i(cyc),
        .wb_ack_o(ack),
        .wb_inta_o(inta0),

        // i2c signals
        .scl_pad_i(scl),
        .scl_pad_o(scl0_o),
        .scl_padoen_o(scl0_oen),
        .sda_pad_i(sda),
        .sda_pad_o(sda0_o),
        .sda_padoen_o(sda0_oen)
    ),
    i2c_top2 (

        // wishbone interface
        .wb_clk_i(clk),
        .wb_rst_i(1'b0),
        .arst_i(rstn),
        .wb_adr_i(adr_i),
        .wb_dat_i(dat_o),
        .wb_dat_o(dat1_i),
        .wb_we_i(we),
        .wb_stb_i(stb1),
        .wb_cyc_i(cyc),
        .wb_ack_o(ack),
        .wb_inta_o(inta1),

        // i2c signals
        .scl_pad_i(scl),
        .scl_pad_o(scl1_o),
        .scl_padoen_o(scl1_oen),
        .sda_pad_i(sda),
        .sda_pad_o(sda1_o),
        .sda_padoen_o(sda1_oen)
    );


    // hookup i2c slave model
    i2c_slave_model #(SADR) i2c_slave (
        .scl(scl),
        .sda(sda)
    );

        // create i2c lines
    delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl),
          m1_scl (scl1_oen ? 1'bz : scl1_o, scl),
          m0_sda (sda0_oen ? 1'bz : sda0_o, sda),
          m1_sda (sda1_oen ? 1'bz : sda1_o, sda);

    pullup p1(scl); // pullup scl line
    pullup p2(sda); // pullup sda line

    initial
      begin
          `ifdef WAVES
             $shm_open("waves");
             $shm_probe("AS",tst_bench_top,"AS");
             $display("INFO: Signal dump enabled ...

");
          `endif

          force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
          //force i2c_slave.debug = 1'b0; // disable i2c_slave debug information

          $display("
status: %t Testbench started

", $time);

//          $dumpfile("bench.vcd");
//          $dumpvars(1, tst_bench_top);
//          $dumpvars(1, tst_bench_top.i2c_slave);

          // initially values
          clk = 0;

          // reset system
          rstn = 1'b1; // negate reset
          #2;
          rstn = 1'b0; // assert reset
          repeat(1) @(posedge clk);
          rstn = 1'b1; // negate reset

          $display("status: %t done reset", $time);

          @(posedge clk);

          //
          // program core
          //

          // program internal registers
          u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
          u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
          u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
          $display("status: %t programmed registers", $time);

          u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
          u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
          $display("status: %t verified registers", $time);

          u0.wb_write(1, CTR,     8'h80); // enable core
          $display("status: %t core enabled", $time);



          $display("***************************");
          $display("test1: access slave (write)");
          $display("***************************");

          // drive slave address
          u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
          u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
          $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );

          // check tip bit
          u0.wb_read(1, SR, q);
          while(q[1])
               u0.wb_read(0, SR, q); // poll it until it is zero
          $display("status: %t tip==0", $time);

          // send memory address
          u0.wb_write(1, TXR,     8'h01); // present slave's memory address
          u0.wb_write(0, CR,      8'h10); // set command (write)
          $display("status: %t write slave memory address 01", $time);

          // check tip bit
          u0.wb_read(1, SR, q);
          while(q[1])
               u0.wb_read(0, SR, q); // poll it until it is zero
          $display("status: %t tip==0", $time);

          // send memory contents
          u0.wb_write(1, TXR,     8'ha5); // present data
          u0.wb_write(0, CR,      8'h10); // set command (write)
          $display("status: %t write data a5", $time);

          // check tip bit
          u0.wb_read(1, SR, q);
          while(q[1])
               u0.wb_read(1, SR, q); // poll it until it is zero
          $display("status: %t tip==0", $time);

          // send memory contents for next memory address (auto_inc)
          u0.wb_write(1, TXR,     8'h5a); // present data
          u0.wb_write(0, CR,      8'h50); // set command (stop, write)
          $display("status: %t write next data 5a, generate 'stop'", $time);

          // check tip bit
          u0.wb_read(1, SR, q);
          while(q[1])
               u0.wb_read(1, SR, q); // poll it until it is zero
          $display("status: %t tip==0", $time);
        
        #WAIT_TIME;
        $display("***************************");
          $display("test2: access slave (read)");
          $display("***************************");

       // drive slave address
       u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
       u0.wb_write(0, CR,     8'h90 ); // set command (start, write)
       $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );

       // check tip bit
       u0.wb_read(1, SR, q);
       while(q[1])
            u0.wb_read(1, SR, q); // poll it until it is zero
       $display("status: %t tip==0", $time);

       // send memory address
       u0.wb_write(1, TXR,     8'h01); // present slave's memory address
       u0.wb_write(0, CR,      8'h10); // set command (write)
       $display("status: %t write slave address 01", $time);

       // check tip bit
       u0.wb_read(1, SR, q);
       while(q[1])
            u0.wb_read(1, SR, q); // poll it until it is zero
       $display("status: %t tip==0", $time);

       // drive slave address
       u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
       u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
       $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );

       // check tip bit
       u0.wb_read(1, SR, q);
       while(q[1])
            u0.wb_read(1, SR, q); // poll it until it is zero
       $display("status: %t tip==0", $time);

       // read data from slave
       u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
       $display("status: %t read + ack", $time);

       // check tip bit
       u0.wb_read(1, SR, q);
       while(q[1])
            u0.wb_read(1, SR, q); // poll it until it is zero
       $display("status: %t tip==0", $time);

       // check data just received
       u0.wb_read(1, RXR, qq);
       if(qq !== 8'ha5)
         $display("
ERROR: Expected a5, received %x at time %t", qq, $time);
       else
         $display("status: %t 1th received %x", $time, qq);

       // read data from slave
       u0.wb_write(1, CR,      8'h68); // set command (read, nack_read,stop)
       $display("status: %t read + ack", $time);

       // check tip bit
       u0.wb_read(1, SR, q);
       while(q[1])
            u0.wb_read(1, SR, q); // poll it until it is zero
       $display("status: %t tip==0", $time);

       // check data just received
       u0.wb_read(1, RXR, qq);
       if(qq !== 8'h5a)
         $display("
ERROR: Expected 5a, received %x at time %t", qq, $time);
       else
         $display("status: %t 2th received %x", $time, qq);

        #WAIT_TIME;
        $display("********************************************************");
          $display("test3: access slave (check invalid slave memory address)");
          $display("********************************************************");


          // drive slave address
          u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
          u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
          $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );

          // check tip bit
          u0.wb_read(1, SR, q);
          while(q[1])
               u0.wb_read(1, SR, q); // poll it until it is zero
          $display("status: %t tip==0", $time);

          // send memory address
          u0.wb_write(1, TXR,     8'h10); // present slave's memory address
          u0.wb_write(0, CR,      8'h10); // set command (write)
          $display("status: %t write slave memory address 10", $time);

          // check tip bit
          u0.wb_read(1, SR, q);
          while(q[1])
               u0.wb_read(1, SR, q); // poll it until it is zero
          $display("status: %t tip==0", $time);

          // slave should have send NACK
          $display("status: %t Check for nack", $time);
          if(!q[7])
            $display("
ERROR: Expected NACK, received ACK
");

          // stop
          u0.wb_write(1, CR,      8'h40); // set command (stop)
          $display("status: %t generate 'stop'", $time);

          // check tip bit
          u0.wb_read(1, SR, q);
          while(q[1])
          u0.wb_read(1, SR, q); // poll it until it is zero
          $display("status: %t tip==0", $time);
        
        #WAIT_TIME;
        $display("********************************************************");
          $display("test4: access slave (write and interrupt acknowledge)");
          $display("********************************************************");

        u0.wb_write(1, CTR,     8'hC0); // enable core and interrupt
        u0.wb_write(1,CR,8'h01);
          $display("status: %t core enabled", $time);

        //TODO
        // drive slave address
          u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
          u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
          $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );

         
        //wait interrupt
        wait(inta0 == 1'b1);
        $display("status: %t interrupt assert",$time);
        u0.wb_read(1,SR,q);
        if(q[1])
          $display("status: %t transfer complete",$time);
        u0.wb_write(0, CR,      8'h01); // set command (IACK)


          // send memory address
          u0.wb_write(1, TXR,     8'h01); // present slave's memory address
          u0.wb_write(0, CR,      8'h10); // set command (write)
          $display("status: %t write slave memory address 01", $time);


        //wait interrupt
        wait(inta0 == 1'b1);
        $display("status: %t interrupt assert",$time);
        u0.wb_read(1,SR,q);
        if(q[1])
          $display("status: %t transfer complete",$time);
          u0.wb_write(0, CR,      8'h01); // set command (IACK)

          // send memory contents
          u0.wb_write(1, TXR,     8'ha5); // present data
          u0.wb_write(0, CR,      8'h10); // set command (write)
          $display("status: %t write data a5", $time);

          //wait interrupt
        wait(inta0 == 1'b1);
        $display("status: %t interrupt assert",$time);
        u0.wb_read(1,SR,q);
        if(q[1])
          $display("status: %t transfer complete",$time);
        u0.wb_write(0, CR,      8'h01); // set command (IACK)

         
          // send memory contents for next memory address (auto_inc)
          u0.wb_write(1, TXR,     8'h5a); // present data
          u0.wb_write(0, CR,      8'h50); // set command (stop, write)
          $display("status: %t write next data 5a, generate 'stop'", $time);

          //wait interrupt
        wait(inta0 == 1'b1);
        $display("status: %t interrupt assert",$time);
        u0.wb_read(1,SR,q);
        if(q[1])
          $display("status: %t transfer complete",$time);
        u0.wb_write(0, CR,      8'h01); // set command (IACK)

          #250000; // wait 250us
          $display("

status: %t Testbench done", $time);
          $finish;
      end

endmodule

module delay (in, out);
  input  in;
  output out;

  assign out = in;

  specify
    (in => out) = (600,600);
  endspecify
endmodule

　　以新添加的中断测试为例。这个case是根据test1改动而来的，区别就是将不断读取寄存器来判断上一指令是否响应完成改为等待中断+读取状态寄存器方式。后者不会过多占用CPU的资源，从软件从面来讲也适用于带有调度算法的操作系统应用。在case开始前启动中断使能并写IACK比特位清除之前的中断标志位。之后在每次写CR后通过下段代码完成等待中断等系列操作。

//wait interrupt
wait(inta0 == 1'b1);
$display("status: %t interrupt assert",$time);
u0.wb_read(1,SR,q);
if(q[1])
$display("status: %t transfer complete",$time);
u0.wb_write(0, CR, 8'h01); // set command (IACK)

　　这部分对应的波形如下，可见中断输出信号inta0被拉高多次。2字节写操作完成。

 五、总结

　　折腾折腾还是有帮助的。之后有打算在此基础上进一步深入，比如搭建基于UVM的验证环境来重新验证这个IP、添加更多的case覆盖所有的features、将interface改成APB bus。

六、参考

1  WISHBONE I2C Master Core下载地址： https://opencores.org/projects/i2c

2 Candence $shm_open $shm_probe 函数_Holden_Liu的博客-CSDN博客

https://blog.csdn.net/holden_liu/article/details/91376709