脉冲边沿检测的实现

module edge_detect(clk, rst_n, trig_in, pose_detect, nege_detect);

input        clk;        //输入时钟
input        rst_n;        //复位信号
input        trig_in;    //输入，待检测的边沿脉冲
output        pose_detect;//输出，上升沿检测
output        nege_detect;//输出，下降沿检测

reg            trig_r0, trig_r1, trig_r2;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
    begin
        trig_r0 <= 1'b0;
        trig_r1 <= 1'b0;
        trig_r2 <= 1'b0;
    end
    else
    begin
        trig_r0 <= trig_in;
        trig_r1 <= trig_r0;
        trig_r2 <= trig_r1;
    end
end

assign pose_detect = (trig_r1) & (!trig_r2);    //脉冲上升沿检测
assign nege_detect = (!trig_r1) & (trig_r2);    //脉冲下降沿检测

endmodule