尽量保持原文，但为了让摘要更简洁，个人做了小小的更改。
1.10-bit addressing allows 1024 additional slave addresses.
2.The High-speed mode allows an increase in the bit rate up to 3.4 Mbit/s.
3.The Fast-mode allows a fourfold increase of bit rate-up to 400 kbit/s.
4.Fast-mode devices are downwards compatible i.e. they can be used in a 0 to 100 kbit/s I2C-bus system.
5.Each device connected to the bus is software addressable
6.masters can operate as master-transmitters or as master-receivers
7.It's true multi-master bus including collision detection and arbitration to prevent data corruption
8.Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 kbit/s in the Standard-mode
9.I2C-bus interface is already integrated on-chip.
10.The simple 2-wire serail I2C-bus minimizes interconnections so ICs have fewer pins and there are not so many PCB tracks.
11.Devices communicating with each other on a serial bus must have some form of protocol which avoids all possibilities of confusion, data loss and blockage of information.
12.The system must not be dependent on the devices connected to it
13.if different devices with different clock speeds are connected to the bus, the bus clock source must be defined.
14.Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data.
15.A master is the device which initiates a data transfer on the bus and generats the clock signals to permit that transfer.
16.any device addressed is considered a slave.
17.The I2C-bus is a multi-master bus.This means that more than one device capable of controlling the bus can be connected to it.
18.the master generates the timing and terminates the transfer.
19.arbitration procedure relies on the wired-AND connection of all I2C interfaces to the I2C-bus.
20.each master generates its own clock signals when transferring data on the bus.
21.If two or more masters try to put information onto the bus, the first to produce a 'one' when the other produces a 'zero' will lose the arbitration.
22.Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding-down the clock line, or by another master when arbitration occurs.
23.The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function.
24.One clock pulse is generated for each data bit transfered.
25.The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.
26.A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition.
27.A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.
28.The bus stays busy if a repeated START is generated instead of a STOP condition.
29.Data is transfered with the most significant bit (MSB) first.
30.If a slave can't receive or transmit another complete byte of data, it can hold the clock line SCL LOW to force the master into a wait state.
31.The acknowledge-related clock pulse is generated by the master.
32.The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse.
33.The receiver must pull down the SDA line during the acknowledge clock pulse
34.When a slave doesn't acknowledge the slave address, the data line must be left HIGH by the slave.The master then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.(个人理解：从机想要接收数据，但是它还没准备好，就在第9时钟SDA依旧保持高电平，即NACK。之后，主机有两种选择，要么结束，要么重新申请通信的开始）
35.If a slave-reciever does acknowledge the slave address but, some time later in the transfer cannot receive any more data bytes by generating the not-acknowledge on the first byte to follow, the master must again abort the transfer.(个人理解：与34相比，此刻从设备倒是准备好了，但是它自己不愿意接收更多的数据，那主机也只能结束通信了，规范没有提到它可以重新申请新的通信，看来就是不能了。举个日常生活例子：你去超市买车厘子，结果第一次第二次超市都关门，那你有两种选择，1.要么不吃；2.要么再去超市看看开门没有，结果你第3次又去超市，这次超市开门了！不过，老板说车厘子被抢完了，只能明年买了，此时，你只有一种选择，那就是今年不吃了！)
36.If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave.The slave-transmitter must release the data line to allow the master to generates a STOP or repeated START condition.(个人理解：类似与SOC读取传感器数据的过程，传感器发数据，SOC回ACK，传感器发数据，SOC回ACK。。突然有一天再发数据的时候，SOC没回ACK，传感器说认为“哦，我懂了，你不想和我玩了”，然后它很识趣的将总线控制权交给了SOC，因为只有这样可以让SOC找新的小伙伴玩)
37.Data is only valid during the HIGH period of the clock.
38.a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period.(个人理解：类似于网络课堂，老师在网络教课，能看见每一个学生的在线情况，如果有一个掉线（SCL HIGH to LOW），那么全班都得等他（all devices SCL HIGH to LOW）,然后老师再次询问全班是否准备好了，如果准备好（able to alter LOW to HIGH）,那么就开始讲课(all devices SCL LOW to HIGH) )
39.A master that loses the arbitration clock pulses until the end of the byte in which it loses the arbitration.
40.The losing master must therefore switch over immediately to its slave mode.
41.arbitration isn't allowed between: A repeated START condition and a data bit / A STOP condition and a data bit / A repeated START condition and a STOP condition.
42.The speed of any master is thereby adapted to the internal opearating rate of this device.(个人理解：主机可以说停就停，说开始就开始，但它也不是可以为所欲为的，一旦选定了从设备，那么通信速度就要受到从设备的制约。)
43.if a master still wishes to communicate on the bus, it can generate a repeated START condition and address another slave without first generating a STOP condition.
44.During a change of direction within a transfer, the START condition and the slave address are both repeated.(个人理解：我觉得这句挺关键的，改变方向就要重复发送开始信号和从设备地址）
45.If a master receiver sends a repeated START condition, it has previously sent a not-acknowledge.
46.After the START condition and slave address is repeated, data can be transferred.