xilinx 7系列芯片不再支持LVDS33电平,在VCCO电压为3.3V的情况下无法使用LVDS25接口。
有些设计者想通过在软件中配置为LVDS25,实际供电3.3V来实现LVDS33也是无效的,原因是xilinx 7系列芯片在IO配置方面增加了过压保护,因而无法通过欺骗综合软件的方式强行配置IO,具体参见
7-Series SelectIO Resources Guide, page 100, Note 2 states:
"if the voltage exceeds 2.85V, the outputs will be in a high-Z state. The device should always be operated within the recommended operating range as specified in the 7 series FPGA data sheets."
虽然在VCCO为3.3V情况下无法输出LVDS25,但可以作为输入进行使用,具体参见AR#43989 https://www.xilinx.com/support/answers/43989.html
参考:
1:https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/LVDS-Interface/td-p/777086
2:https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/LVDS-LVDS-25-Problem-on-Zynq/td-p/645481
3: https://www.xilinx.com/support/answers/43989.html