【分享】居家办公条件下，如何在VCK190的SD启动模式下进行JTAG启动和调试
作者: 付汉杰 hankf@xilinx.com hankf@amd.com
办公室有VCK190单板，运行在SD启动模式下，能进入Linux。但是现在在家办公，不能更改VCK190单板启动模式。
现在需要运行Standalone程序。于是我希望像MPSoC一样，当Versal的A72停留在U-Boot界面下，Vitis能以Jtag运行Standalone程序。实际测试后，发现不行。Vitis开始以Jtag调试程序后，A72启动到了Linux下。
Vitis XSCT Console报告错误“Configuration timed out waiting for SBI_BUSY”， 详细信息如下。
sct% XSDB Server URL: TCP:localhost:44296
xsct% XSDB Server Channel: tcfchan#0
INFO: [Hsi 55-2053] elapsed time for repository (/proj/Xilinx/Vitis/2021.2/data/embeddedsw) loading 0 seconds
attempting to launch hw_server
****** Xilinx hw_server v2021.2.0
**** Build date : Oct 6 2021 at 23:40:43
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application
INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121
initializing
Error while launching program:
Configuration timed out waiting for SBI_BUSY
Configuration timed out waiting for SBI_BUSY
经过研究，可以在XSCT界面下，更改A72的启动模式，并且可以下载BOOT.BIN执行。下面是相关命令。
connect
for {set i 0} {$i < 20} {incr i} {
if { [ta]!=""} break;
after 50
}
targets -set -nocase -filter {name =~ "*Versal*"}
targets
# Enable ISO
mwr -force 0xf1120000 0xffbff
# Switch boot mode
mwr 0xf1260200 0x0100
mrd 0xf1260200
# Set MULTIBOOT address to 0
mwr -force 0xF1110004 0x0
# Perform reset
tar -set -filter {name =~ "PMC"}
rst
# Expect BOOT MODE (Bits [15:12]): 0000 after execution.
device status jtag_status
targets -set -nocase -filter {name =~ "*Versal*"}
targets
puts stderr "INFO: Downloading BIN file: BOOT.BIN to the target."
device program "BOOT.BIN"
after 2000
stop
after 2000
记录信息如下：
xsct% xsct% source versal-program-boot.tcl
INFO: Downloading BIN file: BOOT.BIN to the target.
initializing
0% 0MB 0.0MB/s ??:?? ETA
53% 0MB 1.7MB/s ??:?? ETA
100% 1MB 1.6MB/s 00:01
xsct% Info: Cortex-A72 #0 (target 6) Stopped at 0x15c0 (External Debug Request)
xsct% Info: MicroBlaze PPU (target 9) Stopped at 0xf023a5e8 (Stop)
xsct% Info: MicroBlaze PSM (target 11) Stopped at 0xffc097cc (Stop)
同样，更改A72的启动模式，Vitis能以Jtag运行Standalone程序。
参考文档
Versal: Device Programming/Booting Debug Checklist
Versal ACAP Embedded Design Tutorial -- Boot and Configuration