lab 02 闪耀灯和流水灯
这个实验主要是建立上图所示的模块。LEDG3闪烁，LEDG2-0流水。KEY0复位。
代码
flash_module.v
1 /**
2 * File name: flash_mocule.v
3 *
4 */
5
6 module flash_module
7 (
8 clk, rst_n, led_out
9 );
10
11 input clk;
12 input rst_n;
13 output led_out;
14
15 parameter T50MS = 22'd2_500_000;
16
17 reg [21:0] count;
18
19 always @(posedge clk or negedge rst_n)
20 if (!rst_n)
21 count <= 22'd0;
22 else if (count == T50MS)
23 count <= 22'd0;
24 else
25 count <= count + 1'b1;
26
27 reg rled_out;
28
29 always @(posedge clk or negedge rst_n)
30 if (!rst_n)
31 rled_out <= 1'b0;
32 else if (count == T50MS)
33 rled_out <= ~rled_out;
34
35 assign led_out = rled_out;
36
37 endmodule
38
run_module.v
1 /**
2 * File name: run_mocule.v
3 *
4 */
5
6 module run_module
7 (
8 clk, rst_n , led_out
9 );
10
11 input clk;
12 input rst_n;
13 output [2:0] led_out;
14
15 parameter T1MS = 50_000;
16
17 reg [15:0] count;
18
19 always @(posedge clk or negedge rst_n)
20 if (!rst_n)
21 count <= 16'd0;
22 else if (count == T1MS)
23 count <= 16'd0;
24 else
25 count <= count + 1'b1;
26
27
28 reg [9:0] count_ms;
29
30 always @(posedge clk or negedge rst_n)
31 if (!rst_n)
32 count_ms <= 10'd0;
33 else if (count_ms == 10'd100)
34 count_ms <= 10'd0;
35 else if (count == T1MS)
36 count_ms <= count_ms + 1'b1;
37
38
39 reg [2:0] rled_out;
40
41 always @(posedge clk or negedge rst_n)
42 if (!rst_n)
43 rled_out <= 3'b001;
44 else if (count_ms == 10'd100)
45 begin
46 if (rled_out == 3'b000)
47 rled_out <= 3'b001;
48 else
49 rled_out <= {rled_out[1:0], 1'b0};
50 end
51
52 assign led_out = rled_out;
53
54 endmodule
55
56
19-25行是1ms的计数器，28-36是基于count的100ms的计数器。39-50是3-bit的移位操作。44行表示每隔100ms移位一次。49行是移位代码。
mix_module.v
1 /**
2 * File name: mix_module.v
3 * Function: moving lamp + flash lamp,time interval = 0.1s.
4 * Pins: KEY0-rst_n, LEDG3-0
5 * Target board: DE2.
6 * Software: Quartus II 9.1 sp1
7 * ----------------------------
8 * yf.x
9 * 7-11-2011
10 *
11 */
12
13 module mix_module
14 (
15 CLOCK_50, LEDG, KEY
16 );
17
18 input CLOCK_50;
19 input [0:0] KEY;
20 output [3:0] LEDG;
21
22 flash_module U1
23 (
24 .clk (CLOCK_50),
25 .rst_n (KEY[0]),
26 .led_out (LEDG[3])
27 );
28
29 run_module U2
30 (
31 .clk (CLOCK_50),
32 .rst_n (KEY[0]),
33 .led_out (LEDG[2:0])
34 );
35
36 endmodule
37
38
RTL图
