• Altera Coding Style 之状态机


    Quartus II把某段代码识别为状态机是有一些约束条件的,关键是让综合工具“认识”你的代码。

    …Ensuring that your synthesis tools recognize a piece of code as a state machine …

    一、建议做法

    1、保证分支完备。

          Assign default values to outputs derived from the state machine so that synthesis does not generate unwanted latches.

    2、状态机代码尽量保持独立,与其他逻辑分开写。

          Separate the state machine logic from all arithmetic functions and data paths, including assigning output values.

    3、If your design contains an operation that is used by more that one state, define the operation outside the state machine and cause the output logic of the state machine to use this value.

    4、使用单一的复位信号;若过频繁地使用复位或者置位,Qii很可能把代码综合成普通逻辑。

          Use a simple asynchronous or synchronous reset to ensure a defined power-up state. If your state machine design contains more elaborate reset logic, such as both an asynchronous reset and asynchronous load, the Quartus II software generates regular logic rather thar inferring a state machine.

           另外,虽然影响很小,但是Altera不建议直接给状态变量赋整数值,最好用 parameter 或者 `define。

           Altera recommends against the direct use of integer values for state variables, such as next_state <= 0. However, using an integer does not prevent inference in the Quartus II software.

    二、禁止做法

    但是,以下做法是绝对禁止的。

    1、No state machine is inferred in the Quartus II software if the stare transition logic use arithmetic similar to that in the following example:

               case (state)

                    0: begin

                        if (ena) next_state <= state + 2;

                        else next_state <= state + 1;

                     end

                      1: begin

                       …

                 endcase

            文档的说法不是很明确,我猜测是不能在分支里使用state。

    2、No state machine is inferred in the Quartus II software if the state machine  variable is an output.

    3、No state machine is inferred in the Quartus II software for signed variables.

    三、判断方法

    判断某段代码是否被综合为状态机,可查看编译报告中的 Analysis & Synthesis

    … the state machine si implemented as regular logic gates and registers, and the state machine is not listed as a state machine in the Analysis & Synthesis section of the Quartus II Compilation Report.

    四、举例说明

    以下是Altera提供的一个二段式的状态机代码:

    $V_%YK{2V]19(W`N9U0XSDP

    @F@`0UFG91@CE9CTC{{X3L0

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  • 原文地址:https://www.cnblogs.com/freshair_cnblog/p/2638186.html
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