内核默认的运行地址为PHY_OFFSET+0x8000，即物理地址开始后的0x8000字节处，前面是留给参数用的。参数以atag方式存储，默认放在0x100偏移位置。
http://blog.chinaunix.net/uid-20451980-id-1945241.html
Linux kernel分析（一）
注：本文为Stephen Du原创，转载请注明
一直想把自己自毕业以来学习Linux kernel的点点滴滴进行一次整理，却总是因工作繁忙而一再推迟。最近把kernel知识进行了一次全面的回顾，因此下定决心将这件事情做好。
本文只针对ARM平台的源码分析并且并不包括bootloader的部分，也就是说只分析kernel内的“标准”代码。闲话少说，正式开始。
bootloader完成基本的硬件初始化后，就开始执行arch/arm/kernel/head.S下的汇编代码，紧接着执行arch/arm/kernel/head-common.S，最后跳转到init/main.c中的start_kernel()函数。现在从arch/arm/kernel/head.S入手，看看这里做了什么。
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
以下开始的代码都运行于物理地址空间中并未进入虚地址空间，因为MMU还没有开启！（对于逻辑地址，线性地址，虚地址，物理地址，实模式，保护模式等基本概念此处不会解释）
宏 位置 默认值 说明
KERNEL_RAM_VADDR arch/arm/kernel/head.S
0xc0008000 kernel在RAM中的的虚拟地址
KERNEL_RAM_PADDR arch/arm/kernel/head.S PHYS_OFFSET+0x00008000 kernel在RAM中的的物理地址
PAGE_OFFSET include/asm-arm/memeory.h
0xc0000000 内核空间的起始虚拟地址
TEXT_OFFSET arch/arm/Makefile
0x00008000 内核相对于存储空间的偏移
TEXTADDR arch/arm/kernel/head.S
0xc0008000 kernel的起始虚拟地址
PHYS_OFFSET include/asm-arm/arch-xxx/memory.h 平台相关 RAM的起始物理地址
KERNEL_START KERNEL_RAM_VADDR Kernel被copy进RAM的地址（非XIP的情况如此，但是XIP时候KERNEL_START！=KERNEL_RAM_VADDR）
PHYS_OFFSET是RAM的物理地址，内核规定必须是2M对齐的
25 #if (PHYS_OFFSET & 0x001fffff)
26 #error "PHYS_OFFSET must be at an even 2MiB boundary!"
27 #endif
28 KERNEL_RAM_VADDR定义了经过映射后的内核镜像的virtual地址（link地址），PAGE_OFFSET=3G边界
KERNEL_RAM_PADDR定义了内核镜像的物理地址。
问题：内核镜像为什么一定要映射到高3G的地址上呢？不映射不行吗？
答案：多进程要求多个虚拟地址空间并存，而物理上内存空间只有一个，因此必须将各个进程的虚空间进行动态映射到同一个物理空间上；另一个方面，不同机器环境下，物理内存大小不尽相同（可能太大也可能太小了），必须通过映射屏蔽这些差异以便让进程看不到差异的使用4G（32bit环境）的地址空间！内核属于一个特殊的“进程”（并不是一个进程那么简单），也必须工作于虚地址空间之下（CPU处于实模式下只能寻址有限的物理地址空间），因此需要将物理地址映射到3G（这个3G并不是一定的，可以通过内核编译选项更改，但是通常都是3G）边界的虚地址之上运行，这样基地址+偏移量的寻址思想便可以无缝的使用了！此处答案为本人个人根据现有知识的理解，可能存在错误！
29 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
30 #define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET)
经过映射后的内核镜像的地址必须是1M对齐的！
40 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 //The virtual addr of the kernel need to be 1M align
41 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
42 #endif
定义了临时page table的存放地址（虚地址）0xC000000 - 0x4000
43 swapper_pg_dir
44 .globl swapper_pg_dir
45 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 @The temp page table base addr is here(0xC000000 - 0x4000)
46 该macro用于获取临时page table的物理地址
47 .macro pgtbl, rd
48 ldr d, =(KERNEL_RAM_PADDR - 0x4000)
49 .endm
50 XIP是片内执行的意思；针对某些存在NOR flash扩展的系统内核镜像是直接存放在XOR flash上运行的，因此镜像的地址应该是NOR flash的地址而不是RAM的地址。
51 #ifdef CONFIG_XIP_KERNEL
52 #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
53 #define KERNEL_END _edata_loc
54 #else
55 #define KERNEL_START KERNEL_RAM_VADDR
56 #define KERNEL_END _end
57 #endif
第一阶段：
这一段是bootloader进入kernel的一个入口。在进入该函数之前，整个硬件系统至少需要初始化以下的状态：
1）MMU必须关闭（page
table还没有建立，不能进行虚地址转实地址，CPU工作与相对寻址状态，CP指向的是物理地址）
2)D-cache是CPU的数据cache必须处于关闭状态；I-cache是命令cache可以开也可以关闭！
3）R0由bootloader必须清零；R1由bootloader设置为machine的number（这个是什么，可以查看内核的ARM boot文档arch/arm/tools/mach-types）；R2放置atag指针，bootloader在初始化过程中会将kernel必需的参数搜集并放入该atag list中并将这个地址传递给kernel以便在进入kernel后使用
77 .section ".text.head", "ax"
78 .type stext,
%function
这里定义了由bootloader进入内核的入口stext！关键的部分来了，哈哈哈
79 ENTRY(stext)
由于要做一些底层的初始化，因此先将CPU切入SVC模式并关闭中断（由于中断向量表以及异常向量表并未建立，CPU无法响应中断请求！）
80 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
81
@ and irqs disabled
通过协处理器获取处理器ID
82 mrc
p15, 0, r9, c0, c0 @ get
processor id
此处需要确定CPU的类型才能进行相应的初始化操作
83 bl __lookup_processor_type @ r5=procinfo r9=cpuid
84 movs r10, r5 @ invalid processor (r5=0)?
85 beq
__error_p
@ yes, error 'p'
根据内核中预置的信息，判断当前的board是哪个来确定存储器扩展以及扩展的外设有哪些
86 bl __lookup_machine_type @ r5=machinfo
87 movs r8, r5 @ invalid machine (r5=0)?
88 beq
__error_a
@ yes, error 'a'
此处会去校验atag的内容
89 bl
__vet_atags
这里非常重要！由于CPU要开启MMU进入虚地址执行模式，因此必须先建立一个临时的page table（临时的意思是将来会这个table将会被抛弃，重新建立）
90 bl
__create_page_tables
这一句十分重要也值得去细细推敲，看似没有什么用途，但是在后边开启MMU后进入虚地址空间（link地址）的部分至关重要！因为，该伪指令会将__switch_data对应的虚地址加载给r13寄存器，后面会通过将r13加载进pc（指令计数器）达到进入虚地址模式的目的！也就是说此前的所有代码工作于PIC（position independent code），并没有使用link地址，理解这一点很重要！
99 ldr r13, __switch_data
@ address to jump to
__mmap_switched(This is not PIC addr that means:it is a absolute addr in the
kernel image, another words virtual addr) after the MMU switched on and return
here which start execute code in the virtual space!!!!!!!!!!!!!!!!!!!!!!!!!!
100
@ mmu has been enabled
page table已经建立准备开启MMU
101 adr lr,
__enable_mmu @ return
(PIC) address
执行清除CPU cache以及TLB（table
lookup buffer是MMU的高速缓冲区，提供高速虚实地址转换，原理是将以前的转换结果放在这个buffer当中，如果请求的地址在这里则不做全局搜索）的工作
102 add pc, r10, #PROCINFO_INITFUNC @Call the __cpu_flush to clear I-cache-D-cache TLB related registered as PROCINFO_INITFUNC
103 @After __enable_mmu start to exwcute __switch_data by mov pc, r13 in __enable_mmu
104
多CPU的系统暂时不分析！呵呵
105 #if defined(CONFIG_SMP)
106 .type secondary_startup, #function
107 ENTRY(secondary_startup)
108 /*
109 * Common entry point for secondary CPUs.
110 *
111 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
112 * the processor type - there is no need to check the machine type
113 * as it has already been validated by the primary processor.
114 */
115 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
116 mrc p15, 0, r9, c0, c0 @ get processor id
117 bl __lookup_processor_type
118 movs r10, r5 @ invalid processor?
119 moveq r0, #'p' @ yes, error 'p'
120 beq __error
121
122 /*
123 * Use the page tables supplied from __cpu_up.
124 */
125 adr r4, __secondary_data
126 ldmia r4, {r5, r7, r13} @ address to jump to after
127 sub r4, r4, r5 @ mmu has been enabled
128 ldr r4, [r7, r4] @ get secondary_data.pgdir
129 adr lr, __enable_mmu @ return address
130 add pc, r10, #PROCINFO_INITFUNC @ initialise processor
131 @ (return control reg)
132
133 /*
134 * r6 = &secondary_data
135 */
136 ENTRY(__secondary_switched)
137 ldr sp, [r7, #4] @ get secondary_data.stack
138 mov fp, #0
139 b secondary_start_kernel
140
141 .type __secondary_data, %object
142 __secondary_data:
143 .long .
144 .long secondary_data
145 .long __secondary_switched
146 #endif /* defined(CONFIG_SMP) */
147
开启MMU的函数
155 .type __enable_mmu, %function
156 __enable_mmu:
157 #ifdef CONFIG_ALIGNMENT_TRAP
158 orr r0, r0, #CR_A
159 #else
160 bic r0, r0, #CR_A
161 #endif
162 #ifdef CONFIG_CPU_DCACHE_DISABLE
163 bic r0, r0, #CR_C
164 #endif
165 #ifdef CONFIG_CPU_BPREDICT_DISABLE
166 bic r0, r0, #CR_Z
167 #endif
168 #ifdef CONFIG_CPU_ICACHE_DISABLE
169 bic r0, r0, #CR_I
170 #endif
此处MMU相关的设置，本人没有细究，有情趣的可以研究研究
171 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) |
172 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) |
173 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) |
174 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
175 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
176 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
177 b __turn_mmu_on
这里真正的开启了MMU并从PIC进入virual地址空间运行！！
190 .align 5
191 .type __turn_mmu_on, %function
192 __turn_mmu_on:
执行延时操作（原因在于协处理器相关操作不能立即生效，需要几个ARM的指令周期后才能工作！）
193 mov r0, r0 @delay for the reason of the ARM execute flow!
194 mcr p15, 0, r0, c1, c0, 0 @ write control reg
195 mrc p15, 0, r3, c0, c0, 0 @ read id reg
196 mov r3, r3 @delay!!!!!for the reason of ARM execute flow!
197 mov r3, r3
@delay!!!!!
该行代码之前pc方的是物理地址，此后pc存放的将是虚地址，也就是phys+0xc000000
198 mov pc, r13
@jump to the __switch_data; r3 contains the virtual addr of
__switch_data, because the MMU is on, so this virtual addr can be
translated into the physical addr automatically!
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
以后的代码在虚地址空间运行！！！！！！！！！！！！！！！！！！！
该函数在PHYS_OFFSET+0x08000-0x4000处创建临时page table
215 .type __create_page_tables, %function
216 __create_page_tables:
217 pgtbl r4 @ Get page table base address r4=0x4000 16K addr
清零内存
222 mov r0, r4 @Back up base page table addr
223 mov r3, #0
224 add r6, r0, #0x4000 @ r6 contains the end of page table addr
225 /***Clear the 16K page table memory to 0*/
226 1: str r3, [r0], #4
227 str r3, [r0], #4
228 str r3, [r0], #4
229 str r3, [r0], #4
230 teq r0, r6
231 bne 1b
232 /**End*/
将内核镜像中的MMU flag数值取出，准备设置page table
233 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ get the mm_mmuflags
此处，为当前物理地址起的1M空间建立映射（1M源于ARM的MMU支持2级page，第一级支持1M的page或者指向2级的entry；由于内核镜像的特殊性，它的segments被放在一级page table的1M page内而不是存放在后面将要讲述的4kpage内）
该语句比较重要，pc此处指向物理地址，右移20次则得到当前物理地址的1M计数（再左移20位就是segment的地址！，相当于清零低20bit）
241 mov r6, pc,
lsr #20 @ start of
kernel section r6=pc>>20 contains section addr and the virt addr == phys
addr
根据上句得出的段计数左移20位算出段地址，并将将低20bit设置成MMU的flag，得到一个map entry！
242 orr r3, r7,
r6, lsl #20 @ flags + kernel base
将map entry数值写回page table相应的位置，以便MMU查表转换的时候使用！这里有一点值得注意：这里，映射前后的地址空间实际上上一样的，因为pc的虚地址跟物理地址重合！r6（可以理解r6的数值为page table的index）之所以左移2bit是由于每个page table的entry占4个字节，然后page entry addr=r4（基地址）+index*4
243 str r3, [r4, r6, lsl #2] @ identity mapping;Reason see r6=pc>>20
244 @ r6 contains the index offset in the page table so multiple 4 get the address of the L1 entry
245 /**Here we need an id to
decide which page entry to write the r3, so we apply multi 4 to get the id*/
这里为内核镜像建立映射（映射的本质是设置page
table entry，让MMU知道如何将虚地址转换成物理地址）；非XIP的时候KERNEL_RAM_VADDR=KERNEL_START
251 add
r0, r4, #(KERNEL_START & 0xff000000) >> 18
//Should firstly right shift 20bits and for the reason of page entry is 4 bytes
size so left s hift 2 then is 18;What is 0xff000000?while not
0xfff00000? Answer is in the next code 0x0f00000+0xff000000=0xfff0000!
252 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! //Attention!r3's content remains as the kernel section map, so
253 //The two virtual addr corresponds to the same phys addr!
254 ldr r6, =(KERNEL_END - 1)
255 add r0, r0, #4 //Point to the next L1 entry!
256 add r6, r4, r6, lsr #18 //Caculate the end of L1 entry
257 1: cmp r0, r6 //Reaching the end of entry?
258 add r3, r3, #1 << 20 //add the segment addr for 1
259 strls r3, [r0], #4
260 bls 1b
261
262 #ifdef CONFIG_XIP_KERNEL
263 /*
264 * Map some ram to cover our .data and .bss areas.
265 */
266 orr r3, r7, #(KERNEL_RAM_PADDR & 0xff000000)
267 .if (KERNEL_RAM_PADDR & 0x00f00000)
268 orr r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000)
269 .endif
270 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18
271 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
272 ldr r6, =(_end - 1)
273 add r0, r0, #4
274 add r6, r4, r6, lsr #18
275 1: cmp r0, r6
276 add r3, r3, #1 << 20
277 strls r3, [r0], #4
278 bls 1b
279 #endif
由于最低1M存放了bootloader传递给kernel的一些参数，因此需要为它建立map这样开启MMU后就可以访问这些参数了。
284 add r0, r4, #PAGE_OFFSET >> 18 @The base virtual addr!
285 orr r6, r7, #(PHYS_OFFSET & 0xff000000)
286 .if (PHYS_OFFSET & 0x00f00000)
287 orr r6, r6, #(PHYS_OFFSET & 0x00f00000)
288 .endif
289 str r6,
[r0]
建好页表返回
332 mov pc, lr
333 .ltorg
334
335 #include "head-common.S"
-------------------------------------------------------
如下为 head.S内容，我做了简单注释
/* head.s是linux解压后的运行的第一个程序。 为保持通用性，与机器相关的代码都应有bootloader完成。 此程序主要完成页表初始化，开启MMU。
stext->__enable_mmu->__turn_mmu_on->ldr pc, __mmap_switched
->__mmap_switched(head-common.S)
->b start_kernel(init/main.c)
以下开始的代码都运行于物理地址空间中并未进入虚地址空间，因为MMU还没有开启！ 宏 位置 默认值 说明 KERNEL_RAM_VADDR arch/arm/kernel/head.S 0xc0008000 kernel在RAM中的的虚拟地址 KERNEL_RAM_PADDR arch/arm/kernel/head.S PHYS_OFFSET+0x00008000 kernel在RAM中的的物理地址 PAGE_OFFSET include/asm-arm/memeory.h 0xc0000000 内核空间的起始虚拟地址 TEXT_OFFSET arch/arm/Makefile 0x00008000 内核相对于存储空间的偏移 TEXTADDR arch/arm/kernel/head.S 0xc0008000 kernel的起始虚拟地址 PHYS_OFFSET include/asm-arm/arch-xxx/memory.h 平台相关 RAM的起始物理地址 KERNEL_START KERNEL_RAM_VADDR Kernel被copy进RAM的地址（非XIP的情况如此， 但是XIP时候KERNEL_START！=KERNEL_RAM_VADDR） */ /* * linux/arch/arm/kernel/head.S * * Copyright (C) 1994-2002 Russell King * Copyright (c) 2003 ARM Limited * All Rights Reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Kernel startup code for all 32-bit CPUs */ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> #include <asm/domain.h> #include <asm/ptrace.h> #include <asm/asm-offsets.h> #include <asm/memory.h> #include <asm/thread_info.h> #include <asm/system.h> #include <asm/pgtable.h> #ifdef CONFIG_DEBUG_LL #include <mach/debug-macro.S> #endif /* swapper_pg_dir是初始（第一个）页表的虚拟地址，放在KERNEL_RAM_VADDR下的16K空间。 KERNEL_RAM_VADDR必须0x8000对齐，kernel在ram中的虚拟地址，一般为0xc0008000。 */ /* * swapper_pg_dir is the virtual address of the initial page table. * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect * the least significant 16 bits to be 0x8000, but we could probably * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. */ #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 #error KERNEL_RAM_VADDR must start at 0xXXXX8000 #endif #define PG_DIR_SIZE 0x4000 #define PMD_ORDER 2 .globl swapper_pg_dir .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE .macro pgtbl, rd, phys add d, phys, #TEXT_OFFSET - PG_DIR_SIZE .endm #ifdef CONFIG_XIP_KERNEL #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) #define KERNEL_END _edata_loc #else #define KERNEL_START KERNEL_RAM_VADDR #define KERNEL_END _end #endif /* 内核运行条件：关闭MMU，关闭D-cache，I-cache无关， r0 = 0 r1 = machine nr r2 = atags or dtb指针 R2放置atag指针，bootloader在初始化过程中会将kernel必需的参数搜集并放入该atag list中 并将这个地址传递给kernel以便在进入kernel后使用 */ /* * Kernel startup entry point. * --------------------------- * * This is normally called from the decompressor code. The requirements * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, * r1 = machine nr, r2 = atags or dtb pointer. * * This code is mostly position independent, so if you link the kernel at * 0xc0008000, you call this at __pa(0xc0008000). * * See linux/arch/arm/tools/mach-types for the complete list of machine * numbers for r1. * * We're trying to keep crap to a minimum; DO NOT add any machine specific * crap here - that's what the boot loader (or in extreme, well justified * circumstances, zImage) is for. */ .arm __HEAD ENTRY(stext) THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. THUMB( bx r9 ) @ If this is a Thumb-2 kernel, THUMB( .thumb ) @ switch to Thumb now. THUMB(1: ) setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode @ and irqs disabled mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? THUMB( it eq ) @ force fixup-able long branch encoding beq __error_p @ yes, error 'p' #ifndef CONFIG_XIP_KERNEL adr r3, 2f ldmia r3, {r4, r8} sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) add r8, r8, r4 @ PHYS_OFFSET #else ldr r8, =PHYS_OFFSET @ always constant in this case #endif /* * r1 = machine no, r2 = atags or dtb, * r8 = phys_offset, r9 = cpuid, r10 = procinfo */ bl __vet_atags #ifdef CONFIG_SMP_ON_UP bl __fixup_smp #endif #ifdef CONFIG_ARM_PATCH_PHYS_VIRT bl __fixup_pv_table #endif bl __create_page_tables /* * The following calls CPU specific code in a position independent * manner. See arch/arm/mm/proc-*.S for details. r10 = base of * xxx_proc_info structure selected by __lookup_processor_type * above. On return, the CPU will be ready for the MMU to be * turned on, and r0 will hold the CPU control register value. */ ldr r13, =__mmap_switched @ address to jump to after @ mmu has been enabled adr lr, BSYM(1f) @ return (PIC) address mov r8, r4 @ set TTBR1 to swapper_pg_dir ARM( add pc, r10, #PROCINFO_INITFUNC ) THUMB( add r12, r10, #PROCINFO_INITFUNC ) THUMB( mov pc, r12 ) 1: b __enable_mmu ENDPROC(stext) .ltorg #ifndef CONFIG_XIP_KERNEL 2: .long . .long PAGE_OFFSET #endif /************************************************************************/ /* 建立初始页表。仅仅建立能使内核运行的最小量页，映射在内核区。 */ /* * Setup the initial page tables. We only setup the barest * amount which are required to get the kernel running, which * generally means mapping in the kernel code. * * r8 = phys_offset, r9 = cpuid, r10 = procinfo * * Returns: * r0, r3, r5-r7 corrupted * r4 = physical page table address */ __create_page_tables: pgtbl r4, r8 @ page table address /* * Clear the swapper page table */ mov r0, r4 mov r3, #0 add r6, r0, #PG_DIR_SIZE 1: str r3, [r0], #4 str r3, [r0], #4 str r3, [r0], #4 str r3, [r0], #4 teq r0, r6 bne 1b ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags /* * Create identity mapping to cater for __enable_mmu. * This identity mapping will be removed by paging_init(). */ adr r0, __enable_mmu_loc ldmia r0, {r3, r5, r6} sub r0, r0, r3 @ virt->phys offset add r5, r5, r0 @ phys __enable_mmu add r6, r6, r0 @ phys __enable_mmu_end mov r5, r5, lsr #SECTION_SHIFT mov r6, r6, lsr #SECTION_SHIFT 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping cmp r5, r6 addlo r5, r5, #1 @ next section blo 1b /* * Now setup the pagetables for our kernel direct * mapped region. */ mov r3, pc mov r3, r3, lsr #SECTION_SHIFT orr r3, r7, r3, lsl #SECTION_SHIFT add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) str r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! ldr r6, =(KERNEL_END - 1) add r0, r0, #1 << PMD_ORDER add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 1: cmp r0, r6 add r3, r3, #1 << SECTION_SHIFT strls r3, [r0], #1 << PMD_ORDER bls 1b #ifdef CONFIG_XIP_KERNEL /* * Map some ram to cover our .data and .bss areas. */ add r3, r8, #TEXT_OFFSET orr r3, r3, r7 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]! ldr r6, =(_end - 1) add r0, r0, #4 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 1: cmp r0, r6 add r3, r3, #1 << 20 strls r3, [r0], #4 bls 1b #endif /* boot 参数地址在r2，或者ram的开始1MB空间（加入参数地址未指定） */ /* * Then map boot params address in r2 or * the first 1MB of ram if boot params address is not specified. */ mov r0, r2, lsr #SECTION_SHIFT movs r0, r0, lsl #SECTION_SHIFT moveq r0, r8 sub r3, r0, r8 add r3, r3, #PAGE_OFFSET add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) orr r6, r7, r0 str r6, [r3] #ifdef CONFIG_DEBUG_LL #ifndef CONFIG_DEBUG_ICEDCC /* * Map in IO space for serial debugging. * This allows debug messages to be output * via a serial console before paging_init. */ addruart r7, r3, r0 mov r3, r3, lsr #SECTION_SHIFT mov r3, r3, lsl #PMD_ORDER add r0, r4, r3 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) cmp r3, #0x0800 @ limit to 512MB movhi r3, #0x0800 add r6, r0, r3 mov r3, r7, lsr #SECTION_SHIFT ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags orr r3, r7, r3, lsl #SECTION_SHIFT 1: str r3, [r0], #4 add r3, r3, #1 << SECTION_SHIFT cmp r0, r6 blo 1b #else /* CONFIG_DEBUG_ICEDCC */ /* we don't need any serial debugging mappings for ICEDCC */ ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags #endif /* !CONFIG_DEBUG_ICEDCC */ #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) /* * If we're using the NetWinder or CATS, we also need to map * in the 16550-type serial port for the debug messages */ add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) orr r3, r7, #0x7c000000 str r3, [r0] #endif #ifdef CONFIG_ARCH_RPC /* * Map in screen at 0x02000000 & SCREEN2_BASE * Similar reasons here - for debug. This is * only for Acorn RiscPC architectures. */ add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) orr r3, r7, #0x02000000 str r3, [r0] add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) str r3, [r0] #endif #endif mov pc, lr ENDPROC(__create_page_tables) .ltorg .align __enable_mmu_loc: .long . .long __enable_mmu .long __enable_mmu_end #if defined(CONFIG_SMP) __CPUINIT ENTRY(secondary_startup) /* * Common entry point for secondary CPUs. * * Ensure that we're in SVC mode, and IRQs are disabled. Lookup * the processor type - there is no need to check the machine type * as it has already been validated by the primary processor. */ setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type movs r10, r5 @ invalid processor? moveq r0, #'p' @ yes, error 'p' THUMB( it eq ) @ force fixup-able long branch encoding beq __error_p /* * Use the page tables supplied from __cpu_up. */ adr r4, __secondary_data ldmia r4, {r5, r7, r12} @ address to jump to after sub lr, r4, r5 @ mmu has been enabled ldr r4, [r7, lr] @ get secondary_data.pgdir add r7, r7, #4 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir adr lr, BSYM(__enable_mmu) @ return address mov r13, r12 @ __secondary_switched address ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor @ (return control reg) THUMB( add r12, r10, #PROCINFO_INITFUNC ) THUMB( mov pc, r12 ) ENDPROC(secondary_startup) /* * r6 = &secondary_data */ ENTRY(__secondary_switched) ldr sp, [r7, #4] @ get secondary_data.stack mov fp, #0 b secondary_start_kernel ENDPROC(__secondary_switched) .align .type __secondary_data, %object __secondary_data: .long . .long secondary_data .long __secondary_switched #endif /* defined(CONFIG_SMP) */ /* * Setup common bits before finally enabling the MMU. Essentially * this is just loading the page table pointer and domain access * registers. * * r0 = cp#15 control register * r1 = machine ID * r2 = atags or dtb pointer * r4 = page table pointer * r9 = processor ID * r13 = *virtual* address to jump to upon completion */ __enable_mmu: #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 orr r0, r0, #CR_A #else bic r0, r0, #CR_A #endif #ifdef CONFIG_CPU_DCACHE_DISABLE bic r0, r0, #CR_C #endif #ifdef CONFIG_CPU_BPREDICT_DISABLE bic r0, r0, #CR_Z #endif #ifdef CONFIG_CPU_ICACHE_DISABLE bic r0, r0, #CR_I #endif mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | domain_val(DOMAIN_IO, DOMAIN_CLIENT)) mcr p15, 0, r5, c3, c0, 0 @ load domain access register mcr p15, 0, r4, c2, c0, 0 @ load page table pointer b __turn_mmu_on ENDPROC(__enable_mmu) /* * Enable the MMU. This completely changes the structure of the visible * memory space. You will not be able to trace execution through this. * If you have an enquiry about this, *please* check the linux-arm-kernel * mailing list archives BEFORE sending another post to the list. * * r0 = cp#15 control register * r1 = machine ID * r2 = atags or dtb pointer * r9 = processor ID * r13 = *virtual* address to jump to upon completion * * other registers depend on the function called upon completion */ .align 5 __turn_mmu_on: mov r0, r0 mcr p15, 0, r0, c1, c0, 0 @ write control reg mrc p15, 0, r3, c0, c0, 0 @ read id reg mov r3, r3 mov r3, r13 mov pc, r3 __enable_mmu_end: ENDPROC(__turn_mmu_on) #ifdef CONFIG_SMP_ON_UP __INIT __fixup_smp: and r3, r9, #0x000f0000 @ architecture version teq r3, #0x000f0000 @ CPU ID supported? bne __fixup_smp_on_up @ no, assume UP bic r3, r9, #0x00ff0000 bic r3, r3, #0x0000000f @ mask 0xff00fff0 mov r4, #0x41000000 orr r4, r4, #0x0000b000 orr r4, r4, #0x00000020 @ val 0x4100b020 teq r3, r4 @ ARM 11MPCore? moveq pc, lr @ yes, assume SMP mrc p15, 0, r0, c0, c0, 5 @ read MPIDR and r0, r0, #0xc0000000 @ multiprocessing extensions and teq r0, #0x80000000 @ not part of a uniprocessor system? moveq pc, lr @ yes, assume SMP __fixup_smp_on_up: adr r0, 1f ldmia r0, {r3 - r5} sub r3, r0, r3 add r4, r4, r3 add r5, r5, r3 b __do_fixup_smp_on_up ENDPROC(__fixup_smp) .align 1: .word . .word __smpalt_begin .word __smpalt_end .pushsection .data .globl smp_on_up smp_on_up: ALT_SMP(.long 1) ALT_UP(.long 0) .popsection #endif .text __do_fixup_smp_on_up: cmp r4, r5 movhs pc, lr ldmia r4!, {r0, r6} ARM( str r6, [r0, r3] ) THUMB( add r0, r0, r3 ) #ifdef __ARMEB__ THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. #endif THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. THUMB( strh r6, [r0] ) b __do_fixup_smp_on_up ENDPROC(__do_fixup_smp_on_up) ENTRY(fixup_smp) stmfd sp!, {r4 - r6, lr} mov r4, r0 add r5, r0, r1 mov r3, #0 bl __do_fixup_smp_on_up ldmfd sp!, {r4 - r6, pc} ENDPROC(fixup_smp) #ifdef CONFIG_ARM_PATCH_PHYS_VIRT /* __fixup_pv_table - patch the stub instructions with the delta between * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and * can be expressed by an immediate shifter operand. The stub instruction * has a form of '(add|sub) rd, rn, #imm'. */ __HEAD __fixup_pv_table: adr r0, 1f ldmia r0, {r3-r5, r7} sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET add r4, r4, r3 @ adjust table start address add r5, r5, r3 @ adjust table end address add r7, r7, r3 @ adjust __pv_phys_offset address str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset mov r6, r3, lsr #24 @ constant for add/sub instructions teq r3, r6, lsl #24 @ must be 16MiB aligned THUMB( it ne @ cross section branch ) bne __error str r6, [r7, #4] @ save to __pv_offset b __fixup_a_pv_table ENDPROC(__fixup_pv_table) .align 1: .long . .long __pv_table_begin .long __pv_table_end 2: .long __pv_phys_offset .text __fixup_a_pv_table: #ifdef CONFIG_THUMB2_KERNEL lsls r6, #24 beq 2f clz r7, r6 lsr r6, #24 lsl r6, r7 bic r6, #0x0080 lsrs r7, #1 orrcs r6, #0x0080 orr r6, r6, r7, lsl #12 orr r6, #0x4000 b 2f 1: add r7, r3 ldrh ip, [r7, #2] and ip, 0x8f00 orr ip, r6 @ mask in offset bits 31-24 strh ip, [r7, #2] 2: cmp r4, r5 ldrcc r7, [r4], #4 @ use branch for delay slot bcc 1b bx lr #else b 2f 1: ldr ip, [r7, r3] bic ip, ip, #0x000000ff orr ip, ip, r6 @ mask in offset bits 31-24 str ip, [r7, r3] 2: cmp r4, r5 ldrcc r7, [r4], #4 @ use branch for delay slot bcc 1b mov pc, lr #endif ENDPROC(__fixup_a_pv_table) ENTRY(fixup_pv_table) stmfd sp!, {r4 - r7, lr} ldr r2, 2f @ get address of __pv_phys_offset mov r3, #0 @ no offset mov r4, r0 @ r0 = table start add r5, r0, r1 @ r1 = table size ldr r6, [r2, #4] @ get __pv_offset bl __fixup_a_pv_table ldmfd sp!, {r4 - r7, pc} ENDPROC(fixup_pv_table) .align 2: .long __pv_phys_offset .data .globl __pv_phys_offset .type __pv_phys_offset, %object __pv_phys_offset: .long 0 .size __pv_phys_offset, . - __pv_phys_offset __pv_offset: .long 0 #endif #include "head-common.S"