Reset of the Card
A card reset is initiated by the interface device,whereupon the card shall respond with an Answer to Reset(ATR).
By the end of the activation of the contacts(RST is in L, VCC powered and stable, I/O in reception mode in the interface device, CLK provided suitable and stable clock),
the card answering asynchronously is ready for reset.
whereupon:于是 (表示某事紧接着另一件事之后发生，通常为结果)
You use whereupon to say that one thing happens immediately after another thing, and usually as a result of it.
Note: The internal state of the card is assumed undefined before reset. Therefore, the design of the card has to avoid improper operations.
In order to continue the dialogue with the card, RST shall be maintained in the state(H/Z) where an answer occurs on I/O.
Reset of a card can be initiated by the interface device at its discretion at any time.
discretion:判断力；判定，考虑周到，谨慎，自由裁量权， 由（某人）斟酌决定
If something happens at someone's discretion, it can happen only if they decide to do it or give their permission.
eg: We may vary the limit at our discretion and will notify you of any change. 我们可酌情决定更改限制，并会将任何变更通知你。
Character Frame
For asynchronous transmission type, the character of frame during answer to reset is like in the following diagram.
A character consists of ten consecutive bits:
--A start bit in state A (L) --(starting bit)
--Eight bits of information, designated B0 to B7 and Conveying a data byte;
--A tenth bit used for odd/even parity checking. --(parity bit)
The interface device transmits a header over five successive bytes designated CLA,INS,P1,P2,P3.
CLA: an instruction class, the value FF is reserved for PPS.协议和参量选择(Protocol and Parameter Selection)
INS: an instruction code in the instruction class.
The instruction code is valid only if the LSB is 0, and the most significant half byte(b5-b8) is neither 6 nor 9.
P1,P2: a reference(eg:address) completing the instruction code.
P3: codes the number n of data bytes(D1...Dn) which are to be transmitted during the command.
During the ATR, the etu shall be equal to 372 clock cycles. 1etu=372/f
Before a character, the circuit I/O shall be at state Z.
When searching for a character, the receiver samples I/O periodically.(周期性的采样I/O) The sampling time shall be less than 0.2etu.
The receiver time origin is the mean(平均的) between the last observation of state Z and the first observation of state A.(1->0)
SIM Tx and Rx
The Tx will start when the tx_en (bit 10 in SIM_CTL0) is 1,there is data in the tx fifo and the last Rx is completed.
The tx_int_mark (bit[8-13] in SIM_CTL2) sets the condition under which the tx_int will happen.
When the data entry (条目) in the tx_fifo is less than tx_int_mark, tx_empty_int will be set. tx_ept_msk (bit[1] in SIM_INT_M)
The Rx will start when the rx_en (bit 9 in SIM_CTL0) is 1,when the last tx is done and there is data coming in from the data input.
The rx_int_mark(bit[0-5] in SIM_CTL2) sets the condition under which the rx_int will happen.
When the data entry (条目) in the rx_fifo is greater than rx_int_mark, rx_full_int will be set. rx_full_msk (bit[0] in SIM_INT_M)
Register SIM_CTL0:
The bit_convention register decides MSB/LSB first transmit/receive in the Tx/Rx serial data.
The logic_level register decides if high electrical level represents logic 1 in Tx/Rx serial data and
odd_parity register bit decides if using odd/even parity in Tx/Rx data.
In the SIM interface module, a timer is also designed to check if the receive portion is idle for a
certain period of time and generate an interrupt when it happens.
In SIM_WDT register, set wdog_rx_tout_en (bit[0]) 1 to enable the wdog rx timeout.
In SIM_WDT1 register, sim_wdt1(bit[0:13]) defines the watch dog count limit for rx timeout(idle period).
Any activity in the Rx portion will reset the timer counting.
SIM_WDT: wdog_rtx_tout_en(bit[1])--enable the rx retransmit watch dog timer. this timer watches when
rx re-transmission is happening and it will flag the unresponsive card int when the data from the sim card is timeout(no data comes back).
wdog_cnt_lmt(bit[2:15])--watch dog timer limit for Rx retransmit.
Retransmission
The SIM card controller supports retransmission upon detecting an error condition.
When character parity is incorrect, the receiver shall transmit an error signal by putting I/O circuit to state A at (10.5+-0.2) etu in receiver time for 1 etu minimum, 2 etu maximum.
Then the receiver shall expect a repetition of the character.
The SIM card controller checks the I/O line from the SIM card 11 bits after the start bit leading edge.
If the detected I/O is a zero(error ACK), it assumes an error occurred and retransmits the byte.
If the error ACK signal is repeated for the programmable number of times specified in the SIM_SEH(tx_retrx_lmt bit[7:4]) register.
The SIM card interface sets the bad Tx parity error bit in the status (SIM_STS0)register and issue an interrupt.
For detecting an error signal, the transmitter shall check the state of the I/O circuit at (11+-0.2) etu in transmitter time(after the leading edge)前沿
-----The correct reception is assumed if the state is Z.
-----The incorrect reception is assumed if the state is A.
After a delay of at least two etu after detection of the error signal, the transmitter shall repeat the character.
For the transmission from the SIM controller to the SIM card, when the SIM controller detects a parity error following the transmission of a data byte,
it performs the following sequence:
-----The SIM card interface retransmits the data.
-----If the retransmission succeeds, it ignores the initial failure.
-----If the retransmission fails for the number of times specified in SIM_SEH(tx_retrx_lmt bit[7:4]),
the SIM card interface sets the bad parity bit tx_prt_err_sts(bit[3]) in (SIM_STS0) and issue an interrupt
and set SIM_INT_M(tx_prt_err_msk bit[3]) 1.
