Possible Causes for PLL Loss of Lock
A phase-locked loop (PLL) can lose lock for a number of reasons. The following are some common causes for the PLL to loselock. If the explanation of these causes do not resolve your issue, submit aservice request to mySupport, Altera's technical online support system.
1.Jitter on PLL input clock is out ofspecification
Excessive jitter on the input clock cancause the PLL to lose lock. For PLL input jitter specification, refer to the DCand Switching Characteristics chapter in the device family handbook.
Since the PLL acts as a low-pass filter,you can use it to filter input jitter as well. The programmable bandwidth feature allows you to control the low-pass response characteristics. To filter higher frequency jitter, use a low bandwidth setting. To track jitter, use ahigh bandwidth setting. Refer to the PLL chapter in the device family handbook to check whether the PLL in that device supports the programmable bandwidth feature.
To check whether jitter is a problem,compare your input clock’s jitter characteristics (in the frequency domain)with the PLL’s bandwidth (reported in the Quartus® II PLL Summary Report file).If your jitter frequency is within the bandwidth or falls near the edge of the bandwidth, it could be coupling through or being slightly amplified (due tojitter peaking).
2.Simultaneous switching noise (SSN)
Excessive switching noise on the clock inputs of the PLL could cause the PLL to lose lock. Switching noise on the inputs is a form of deterministic jitter that is subject to the input jitter specification shown in the device family data sheet.
3.Power supply noise
Excessive noise on the VCCA plane can cause high output jitter and possible loss of lock. VCCA is subject to the same requirements (+/- 5%) as the other device power supplies. Again, you can usethe PLL bandwidth setting to suppress some of the output jitter. Since VCCA powers the voltage controlled oscillator (VCO), noise on this supply could cause the VCO output frequency to fluctuate and cause jitter. A low bandwidth causes the loop to respond slower to the noise being injected by the VCO. In turn, it cannot adjust for this noise and counteract it. A high bandwidth, onthe other hand, allows the loop to respond quickly to the noise and compensatefor it.
4.Input clock stops/glitches or there is asudden phase change
A glitch or stopping of the input clock tothe PLL could cause the PLL to lose lock. The PLL operates by using a feedback loop to track a reference clock. If the reference clock stops, the PLL nolonger has a signal to track. If there is a sudden, drastic phase change of theinput clock, the PLL may not be able to react quickly enough to maintain lock.
5.PLL is reset
Asserting the areset or pllena ports of the PLL causes it to lose lock. These ports reset all the PLL counters and reset the VCO to its nominal value.
6.An attempt has been made to reconfigure thePLL
Once the scanwrite port is asserted, the PLL scan chain is uploaded to the actual counters. The PLL could lose lock during or after PLL reconfiguration if the M counter, N counter, or phase shift settings have changed during the reconfiguration process. Changes to the post-scale counters do not affect the PLL lock signal.
7.Stratix® or Cyclone® PLLs lose lock at lowtemperatures (< -20C)
This is a known issue. For details, see theStratix FPGA Errata Sheet or Table 4 -52 in the DC & Switching Characteristics chapter of the Cyclone Device Handbook.
8.Input clock frequency goes outside the lockrange as reported in the Quartus II PLL Summary Report file
The input clock frequency must stay withinthe minimum and maximum lock frequency.
9.Phase frequency detector (PFD) is disabled using pfdena port
When the PFD is disabled, the loop nolonger tracks changes to the input clock. The PLL output continues to toggle atthe last frequency but drifts to a lower frequency (or higher, depending on theclock setting). The PLL could lose lock since the output clock phase (andfrequency) has drifted outside of the lock window of the PLL.
How the PLL Gains Lock
Upon power up, the PLL VCO's controlvoltage is set to a voltage slightly above VCCA/2. This corresponds to acertain frequency (generally the mid-point of the VCO operating range).Depending on the PLL input frequency and the M counter setting, the VCOattempts to either increase or decrease in frequency to match the PFD inputfrequency (which is fIN/N).
How fast the PLL reacts is dependent on the loop settings of the PLL. Once the PLL gains frequency lock, the PFD tries to match the phase of the input clock to the feedback clock. How closely the phaseis matched is based on the lock window setting (which is determined by theQuartus II software). The lock detect circuitry comes from the PLL loop, which means the clock signals to the PFD are observed to determine if they are close enough in phase (within the lock window setting) for the PLL to be considered locked.
PLL失锁原因
PLL失锁的一些可能原因。
锁相环（PLL）失锁的原因可能有很多。以下是PLL失锁的一些常见原因。如果这些原因的解释不能解决你的问题，可以在Altera的在线技术支持系统MySupport中提交服务请求。
l PLL输入时钟抖动超过规范。
输入时钟有过大的抖动可能引起PLL失锁。PLL的输入抖动规范，参考芯片Handbook 中的DC and Switching Characteristics章节。
由于PLL实际是一个低通滤波器，您也可以使用它来滤掉输入抖动。可编程的带宽特性允许您来控制这个低通响应特性。为了滤掉更高的频率抖动，使用一个低带宽设置；要跟踪抖动，使用一个更高带宽设置。参考芯片Handbook的PLL章节来检查PLL在这个芯片中是否可编程带宽特性。
为了检测抖动是否是个问题，比较输入时钟抖动特性（在频率范围）和PLL带宽（Quartus PLL总结报告的报告）。如果你的抖动频率在这个带宽之内或者带宽的边沿，它可能通过耦合或略有放大（由于抖动峰值）。
l 同步开关噪声（SSN）
PLL时钟输入上过大的转换噪声可以引起时钟失锁。输入上的转换噪声是一个确定性的抖动形式，在芯片datasheet 中提供的输入抖动规格。
电源噪声。
在VCCA上的过大的噪声可以引起高输出抖动，并引起失锁。在其他设备上的VCCA也适用于同样的要求（+/- 5%）。同样，你可以使用PLL带宽设置来镇压一些输出抖动。由于VCCA给压控振荡器（VCO）供电，这电源上的噪声可以引起VCO输出频率波动和引起抖动。由于VCO引入了噪声，低带宽会引起循环响应缓慢。相反，则不能适应这个噪声并抵消它。另一方面，高带宽看可以引起快速噪声响应，并消除它。
l 输入时钟停止/毛刺或者有一个突然的相位变化。
PLL的输入时钟突然停止或有毛刺可以引起PLL失锁。PLL通过一个反馈循环来检测参考时钟。如果PLL输入时钟停止则没有信号来检测。如果输入时钟突然一个相位改变，PLL可能不能快速响应来保持LOCKED稳定。
l PLL复位
使能PLL的复位端口引起失锁。这些管脚复位所有的PLL计数器和复位VCO的正常电压值。
l 已尝试重配置PLL
一旦scanwrite端口有效，PLL的扫描链更新到实际的计数器。如果在重配置过程中M计数器、N计数器、相位移位设置改变，则PLL可能会重配置。改变POST-Scale 计数器不影响锁相环锁定信号。
l Stratix和Cyclone 系列在温度在-20度以下PLL失锁。
l 输入时钟频率超出Quartus PLL总结报告文件中的范围。
l 相位频率检测器PFD禁止使用pfdena端口。
当PFD被禁用，循环不再检测输入时钟的改变，输入时钟在最后一个频率时仍然翻转。但是会漂移到更低（更高，要根据设置）的频率。由于输出时钟频率相位（和频率）已经飘移出PLL的锁存window ，则PLL可能会失锁。
PLL如何获得LOCK？
上电时，PLL的VCO的控制电压设定为略高于VCCA/2。这相当于一个特定的频率（一般的VCO的工作范围的中点）。根据锁相环输入频率和M计数器设置，VCO试图增加或减少频率来匹配PFD输入频率（就是fIN/ N）。
PLL的反应速度有多快取决于PLL的环路设置。一旦PLL获得频率锁定，PFD试图将输入时钟与反馈时钟相位相匹配。相位有多接近是基于lock窗口设定（由Quartus软件确定）。Lock检测电路来自PLL循环，这意味着观察PFD的时钟信号来确定他们在相位上是否有足够的相近（在lock窗口内）才能考虑PLL locked。