基于BASYS2的VHDL程序——数字钟

在编电子表时发现FPGA求余，取模只能针对2的次方。毕竟是数字的嘛！

时钟用到了动态刷新数码管。以一个大于50Hz的速度刷新每一个数码管。

因为数码管只有四个，只写了分针和秒针。

代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock is
    Port ( clk : in  STD_LOGIC;
           seg : out  STD_LOGIC_VECTOR (6 downto 0);
           an : out  STD_LOGIC_VECTOR (3 downto 0));
end clock;

architecture Behavioral of clock is
signal num:STD_LOGIC_VECTOR (3 downto 0);
signal min_h:STD_LOGIC_VECTOR (3 downto 0);
signal min_l:STD_LOGIC_VECTOR (3 downto 0);
signal second_h:STD_LOGIC_VECTOR (3 downto 0);
signal second_l:STD_LOGIC_VECTOR (3 downto 0);
signal an_sel:STD_LOGIC_VECTOR (1 downto 0);
signal cnt:   INTEGER;
signal cnt2:  INTEGER;
signal sclk: STD_LOGIC;
constant a:integer :=8;
begin
process(clk)
begin
if(clk'event and clk='1') then
    if(cnt=25000000) then
        cnt<=0;
        sclk<=not sclk;
    else
        cnt<=cnt+1;
    end if;
end if;
end process;

process(clk)
begin
if(clk'event and clk='1') then
    if(cnt2=100000) then
        cnt2<=0;
        if(an_sel="11") then
            an_sel<="00";
        else
            an_sel<=an_sel+'1';
        end if;
    else
        cnt2<=cnt2+1;
    end if;
end if;
end process;

process(sclk)
begin
if(sclk'event and sclk='1') then
    if(second_h="0101" and second_l="1001") then
        second_h<="0000";
        second_l<="0000";
        min_l<=min_l+'1';
        if(min_h="0101" and min_l="1001") then
            min_h<="0000";
            min_l<="0000";
        elsif(min_l="1001") then
            min_h<=min_h+'1';
            min_l<="0000";
        end if;
    elsif(second_l="1001") then
        second_h<=second_h+'1';
        second_l<="0000";
    else
        second_l<=second_l+'1';
    end if;
end if;
end process;

process(an_sel,second_l,second_h,min_l,min_h)
begin
case an_sel is
when "00"=>an<="0111";num<=second_l;
when "01"=>an<="1011";num<=second_h;
when "10"=>an<="1101";num<=min_l;
when "11"=>an<="1110";num<=min_h;
when others=>null;
end case;

case num  is
        when x"0"=>seg<=b"0000001";
        when x"1"=>seg<=b"1001111";
        when x"2"=>seg<=b"0010010";
        when x"3"=>seg<=b"0000110";
        when x"4"=>seg<=b"1001100";
        when x"5"=>seg<=b"0100100";
        when x"6"=>seg<=b"0100000";
        when x"7"=>seg<=b"0001111";
        when x"8"=>seg<=b"0000000";
        when x"9"=>seg<=b"0000100";
        when others=>null;
end case;
end process;
end Behavioral;

约束文件如下：

NET "clk" LOC = "B8";
NET "an<0>" LOC="K14";
NET "an<1>" LOC="M13";
NET "an<2>" LOC="J12";
NET "an<3>" LOC="F12";
NET "seg<6>" LOC="L14";
NET "seg<5>" LOC="H12";
NET "seg<4>" LOC="N14";
NET "seg<3>" LOC="N11";
NET "seg<2>" LOC="P12";
NET "seg<1>" LOC="L13";
NET "seg<0>" LOC="M12";