固定脉冲宽度信号生成---基于定时器和边沿检测

固定脉冲宽度信号生成---基于定时器和边沿检测

//--------------------------------------------------------------------------------------------------
// fixed by chensimin
//--------------------------------------------------------------------------------------------------
    wire               decoder_0_rst;
    wire               decoder_0_hpd;
    assign decoder_0_rst = decoder_0_control_0[ `BIT_DECODER_CONTROL_0_RESET ];
    assign decoder_0_hpd = decoder_0_control_0[ `BIT_DECODER_CONTROL_0_HPD   ];

//--------------------------------------------------------------------------------------------------
    // rising_phd edge hpd信号同步与上升沿检测

    reg decoder_0_hpd_delay;
    reg decoder_0_hpd_delay_1;
    reg decoder_0_hpd_delay_2;
    wire rising_phd;

    always @(posedge clk_25m or posedge bus_reset)
    begin
        if(bus_reset)
        begin
            decoder_0_hpd_delay    <= 1'b0;
            decoder_0_hpd_delay_1  <= 1'b0;
            decoder_0_hpd_delay_2  <= 1'b0;
        end

        else 
        begin
            decoder_0_hpd_delay    <= decoder_0_hpd;
            decoder_0_hpd_delay_1  <= decoder_0_hpd_delay;
            decoder_0_hpd_delay_2  <= decoder_0_hpd_delay_1;
        end
    end

    assign rising_phd = (!decoder_0_hpd_delay_2) && decoder_0_hpd_delay_1;

//--------------------------------------------------------------------------------------------------

    //rising_rst 复位信号同步与上升沿检测

    reg decoder_0_rst_delay;
    reg decoder_0_rst_delay_1;
    reg decoder_0_rst_delay_2;
    wire rising_rst;

    always @(posedge clk_25m or posedge bus_reset)
    begin
        if(bus_reset)
        begin
            decoder_0_rst_delay    <= 1'b0;
            decoder_0_rst_delay_1  <= 1'b0;
            decoder_0_rst_delay_2  <= 1'b0;
        end

        else 
        begin
            decoder_0_rst_delay    <= decoder_0_rst;
            decoder_0_rst_delay_1  <= decoder_0_rst_delay;
            decoder_0_rst_delay_2  <= decoder_0_rst_delay_1;
        end
    end

    assign rising_rst = (!decoder_0_rst_delay_2) && decoder_0_rst_delay_1;

//--------------------------------------------------------------------------------------------------

    // get 1us 1微妙计数器，计时器开机复位，然后便开始计数，当接收到rising_phd信号后，计数器清零，作为有效计数的起始点

    reg              get_time_1us ;
    reg   [31:0]     m ;
    always @(posedge clk_25m or posedge bus_reset )
    begin
        if(bus_reset)
        begin
            get_time_1us <= 1'b0;
            m <= 0;
        end
        else if(rising_phd)
        begin
            get_time_1us <= 1'b0;
            m <= 0;
        end
        else if(m == 24)
        begin
            get_time_1us <= 1'b1;
            m <= 0;
        end
        else 
        begin
            get_time_1us <= 1'b0;
            m <= m + 1'b1;
        end
    end 

//--------------------------------------------------------------------------------------------------

    // output hdmi_hpd 固定脉宽hpd信号生成模块，hpd信号开机复位并保持低电平，当接收到rising_phd信号触发后
    // hpd信号拉高，并清空计数器，此时作为hpd高电平信号的起点，当k=1000000时候，hpd信号拉低，计数器清零。

    reg              hdmi_hpd ;
    reg   [31:0]     k ;

    always @(posedge clk_25m or posedge bus_reset )
    begin
        if(bus_reset)
        begin
            hdmi_hpd <= 1'b0;
            k <= 0;
        end
        else if(rising_phd)
        begin
            hdmi_hpd <= 1'b1;
            k <= 0;
        end 
        else if(k==1000000)
        begin
            hdmi_hpd <= 1'b0;
            k <= 0;
        end
        else if(get_time_1us)
            k <= k + 1;
    end

//--------------------------------------------------------------------------------------------------

    // get 1us 1微妙计数器，用于另外一个信号的控制

    reg              get_time_1us_1 ;
    reg   [31:0]     i ;
    always @(posedge clk_25m or posedge bus_reset )
    begin
        if(bus_reset)
        begin
            get_time_1us_1 <= 1'b0;
            i <= 0;
        end
        else if(rising_rst)
        begin
            get_time_1us_1 <= 1'b0;
            i <= 0;
        end
        else if(i == 24)
        begin
            get_time_1us_1 <= 1'b1;
            i <= 0;
        end
        else 
        begin
            get_time_1us_1 <= 1'b0;
            i <= i + 1'b1;
        end
    end 

//--------------------------------------------------------------------------------------------------

    // hdmi_reset 复位信号的产生，控制复位信号的宽度

    reg [31:0]     j ;

    always @(posedge clk_25m or posedge bus_reset)
    begin
        if(bus_reset)
        begin
            hdmi_reset <= 1'b0;
            j <= 0;
        end
        else if(rising_rst)
        begin
            hdmi_reset <= 1'b0;
            j <= 0;
        end
        else if(j==8000)
        begin
            hdmi_reset <= 1'b1;
            j <= 0;
        end 
        else if(get_time_1us_1)
            j <= j + 1;
    end