串口发送程序

串口发送程序

以下程序基于KC705开发板，以及猫猫串口网络调试助手验证通过。

1.串口发送

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: chensimin
// 
// Create Date: 2018/12/24 14:06:24
// Design Name: 
// Module Name: tx_funcmod_1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tx_funcmod_1 (

    input    wire          clk,
    input    wire          rst,
    output   reg           txd,
    input    wire          enable,
    output   reg           done,
    input    wire   [7:0]  data

    );


//----------------------------------------------------------------------------------

    //50M Hz
    parameter B115K2 = 14'd10416 ; // formula : ( 1/115200 )/( 1/50E+6 )    

//----------------------------------------------------------------------------------

    reg enable_delay_1;
    reg enable_delay_2;

    always @ (posedge clk or posedge rst) 
    begin
        if(rst)
        begin
            enable_delay_1 <= 1'b0;
            enable_delay_2 <= 1'b0;
        end

        else 
        begin
            enable_delay_1 <= enable;
            enable_delay_2 <= enable_delay_1;
        end
    end

//----------------------------------------------------------------------------------

    assign rising = !enable_delay_2 && enable_delay_1;

//----------------------------------------------------------------------------------

    reg send_one_time;
    
    always @ (posedge clk or posedge rst) 
    begin
        if(rst)
            send_one_time <= 1'b0;
        else if(rising)
            send_one_time <= 1'b1;
        else if(i == 13)
            send_one_time <= 1'b0;
    end

//----------------------------------------------------------------------------------

    reg [3:0]   i;
    reg [13:0]  C1;
    reg [10:0]  D1;

    always @ (posedge clk or posedge rst) 
    begin
        if(rst)
        begin
            i    <=  4'd0 ;
            C1   <=  0    ;
            D1   <=  0    ;
            txd  <=  1'b1 ;
            done <=  1'b0 ;
        end

        else if(send_one_time)
        begin
            case(i)

                0:
                begin
                    D1 <= {2'b11, data, 1'b0};
                    i  <= i + 1'b1;
                end

                1,2,3,4,5,6,7,8,9,10,11:
                begin
                    if( C1 == B115K2 -1 ) 
                    begin 
                        C1 <= 8'd0; 
                        i  <= i + 1'b1; 
                    end
                     
                    else 
                    begin 
                        txd <= D1[i-1]; 
                        C1  <= C1 + 1'b1; 
                    end
                end

                12:
                begin 
                       done <= 1'b1; 
                    i    <= i + 1'b1; 
                end
                     
                 13:
                begin 
                    done <= 1'b0; 
                    i    <= 4'd0; 
                end
            endcase    
        end
    end


//----------------------------------------------------------------------------------

    ila_1 U10 (
        .clk(clk),                    // input wire clk

        .probe0(send_one_time),       // input wire [0:0]  probe0  
        .probe1(rising),              // input wire [0:0]  probe1 
        .probe2(enable),              // input wire [0:0]  probe2 
        .probe3(enable_delay_1),      // input wire [0:0]  probe3 
        .probe4(enable_delay_2),      // input wire [0:0]  probe4 
        .probe5(i),                    // input wire [3:0]  probe5
        .probe6(done)                 // input wire [0:0]  probe6
    );


endmodule

2.串口接收

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: chensimin
// 
// Create Date: 2018/12/24 16:33:17
// Design Name: 
// Module Name: rx_funcmod_1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module rx_funcmod_1 (

    input   wire         clk,
    input   wire         rst,
    input   wire         rxd,
    input   wire         enable,
    output  reg          done,
    output  wire  [7:0]  data

    );


//----------------------------------------------------------------------

    parameter BPS115K2 = 14'd10416 ;
    parameter SAMPLE   = 14'd2604  ;

//----------------------------------------------------------------------

    reg [3 :0]      i;
    reg [13:0]      C1;
    reg [7 :0]      D1;
    reg             done;

    always @ (posedge clk or posedge rst)
    begin
        if(rst)
        begin
            i    <= 4'd0;
            C1   <= 0   ;
            D1   <= 8'd0;
            done <= 1'b0;
        end

        else if(enable)
        begin
            case(i)

                0:
                if( rxd == 1'b0 )
                begin
                    i  <= i  + 1'b1 ;
                    C1 <= C1 + 1'b1 ;
                end

                1:
                if(C1 == BPS115K2 - 1)
                begin
                    C1 <= 8'd0 ;
                    i  <= i + 1'b1;
                end
                else 
                    C1 <= C1 + 1'b1;

                2,3,4,5,6,7,8,9:
                begin
                    if(C1 == SAMPLE) 
                        D1[i-2] <= rxd;

                    if(C1 == BPS115K2-1)
                    begin
                        C1 <= 8'd0;
                        i  <= i + 1'b1;
                    end
                    else 
                        C1 <= C1 + 1'b1; 
                end

                10,11:
                if(C1 == BPS115K2-1) 
                begin 
                    C1 <= 8'd0; 
                    i  <= i + 1'b1; 
                end
                else 
                    C1 <= C1 + 1'b1;

                12:
                begin 
                    done <= 1'b1; 
                    i    <= i + 1'b1; 
                end
                     
                13:
                begin 
                    done <= 1'b0; 
                    i    <= 4'd0; 
                end
            endcase
        end
    end

//----------------------------------------------------------------------

    assign data = D1;

//----------------------------------------------------------------------

    ila_2 U9 (
        .clk(clk),                     // input wire clk

        .probe0(i),                    // input wire [3:0]  probe0  
        .probe1(D1),                   // input wire [7:0]  probe1 
        .probe2(done),                 // input wire [0:0]  probe2 
        .probe3(data),                 // input wire [7:0]  probe3 
        .probe4(enable),               // input wire [0:0]  probe4 
        .probe5(rxd)                   // input wire [0:0]  probe5
    );


endmodule

3.顶层文件

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: chensimin
// 
// Create Date: 2018/12/24 13:40:27
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top (

    input    wire      clk_in1_p,
    input    wire      clk_in1_n,
    output   wire      txd,
    input    wire      rxd


    );


//---------------------------------------------------------------

wire  clk_out1;
wire  locked;

clk_wiz_0 U0 (
    .clk_out1(clk_out1),     
    .locked(locked),       
    .clk_in1_p(clk_in1_p),    
    .clk_in1_n(clk_in1_n)
);    

//---------------------------------------------------------------

wire        reset;
wire        enable;
wire [7:0]  data;
wire        enable_rx;

vio_0 U1 (
  .clk(clk_out1),                 // input wire clk
  .probe_in0(locked),             // input wire [0 : 0] probe_in0
  .probe_out0(reset),             // output wire [0 : 0] probe_out0
  .probe_out1(enable),            // output wire [0 : 0] probe_out1
  .probe_out2(data),              // output wire [7 : 0] probe_out2
  .probe_out3(enable_rx)          // output wire [0 : 0] probe_out3
);

//---------------------------------------------------------------

wire done;

tx_funcmod_1 U2 (

    .clk(clk_out1),
    .rst(reset),
    .txd(txd),
    .enable(enable),
    .done(done),
    .data(data)
);

//---------------------------------------------------------------

ila_0 U3 (
    .clk(clk_out1),     // input wire clk

    .probe0(done),      // input wire [0:0]  probe0  
    .probe1(txd),       // input wire [0:0]  probe1 
    .probe2(data),      // input wire [7:0]  probe2
    .probe3(rx_done),   // input wire [0:0]  probe3 
    .probe4(rx_data)    // input wire [7:0]  probe4
);

//---------------------------------------------------------------

wire          rx_done;
wire [7:0]    rx_data;


rx_funcmod_1 U4 (

    .clk(clk_out1),
    .rst(reset),
    .rxd(rxd),
    .enable(enable_rx),
    .done(rx_done),
    .data(rx_data)
);


endmodule