这几天希望能在Spartan系列新品xc6slx16csg324-2运行带有FFT的软核处理系统，基本系统早就搭建好了。需要做的就是建立一个封装有Xilinx提供的FFT IP的自定义外设。由于Xilinx提供的FFT模块直接是用AXI Stream的接口。
在XPS下，Create or Import a Peripherel，选择使用AXI Stream的接口，而非以前常用的AXI4-lite接口。然后选择使用Verilog语言，允许生成模板，允许自动建立一个ise工程，Stream的字节数为1024点，以便于后面添加FFT。
在工程路径里面，..day9_DataConverterpcoresaxi_stream_ip_test_v1_00_adevlprojnav可以看到一个专门的.xise工程文件。
使用ise打开这个工程，可以看到模板里面，有一对AXI Stream的Master和Slave的接口。在这里我们添加FFT模块，如上图。对它配置，如下图。具体为什么这样配置，不解释了，得好好看他的文档了，下面图中每一页上都有datasheet的链接，可以下载仔细看，74页的节奏。
从上图可以看到，Xilinx提供的FFT用了2对AXI Stream的接口：
1.接受原始数据接口Slave AXI Stream ；
2.转换得到FFT/iFFT的数据输出接口为Master AXI Stream ；
3. 配置接口用于配置各项参数，Slave AXI Stream Config;
4.查询状态接口，用于查询，Master AXI Stream Status.
这样共两对AXI Stream接口。当然每一个接口里面不是将所有的端口都用上了。完整的端口也不是很多，可以查看ARM公司的amba4_axi4_stream_v1_0_protocol_spec.pdf文档。
既然有两对接口，而XPS默认创建的IP只有一对接口，那就全部给修改掉吧，把.v文件、.mpd文件都大修了。同时添加fft的.v文件，还有它的网表文件.ngc。同时还要创建netlist文件夹，放.ngc。具体见
其实我按照这个做了，但XPS最终总是会synthesis成功，而implementation失败。
最后，发现mpd文件里面缺少几个OPTION.
还是，把mpd文件帖出来吧。加粗的地方，是我刚开始没有care过的。后来加了之后才通过，就这个，坑了我两天。
BEGIN axi_stream_ip_test
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION STYLE = MIX
OPTION IP_GROUP = MICROBLAZE:USER
OPTION LONG_DESC = This is for test about AXI stream interface ,note that it is not a BUS.Be aware that the difference between interface and bus.
## Bus Interfaces
BUS_INTERFACE BUS=M_AXIS, BUS_STD=AXIS, BUS_TYPE=INITIATOR
BUS_INTERFACE BUS=S_AXIS, BUS_STD=AXIS, BUS_TYPE=TARGET
BUS_INTERFACE BUS=Status_AXIS, BUS_STD=AXIS, BUS_TYPE=INITIATOR
BUS_INTERFACE BUS=Ctrl_AXIS, BUS_STD=AXIS, BUS_TYPE=TARGET
## Parameters
PARAMETER C_S_AXIS_PROTOCOL = GENERIC, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = S_AXIS
PARAMETER C_S_AXIS_TDATA_WIDTH = 32, DT = integer, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = S_AXIS
PARAMETER C_M_AXIS_PROTOCOL = GENERIC, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = M_AXIS
PARAMETER C_M_AXIS_TDATA_WIDTH = 32, DT = integer, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = M_AXIS
PARAMETER C_Ctrl_AXIS_PROTOCOL = GENERIC, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = Ctrl_AXIS
PARAMETER C_Ctrl_AXIS_TDATA_WIDTH = 32, DT = integer, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = Ctrl_AXIS
PARAMETER C_Status_AXIS_PROTOCOL = GENERIC, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = Status_AXIS
PARAMETER C_Status_AXIS_TDATA_WIDTH = 32, DT = integer, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = Status_AXIS
## Peripheral ports
PORT ACLK = "", DIR=I, SIGIS=CLK,BUS=S_AXIS:M_AXIS:Ctrl_AXIS:Status_AXIS
PORT S_AXIS_ARESETN = ARESETN, DIR=I, SIGIS = RST
PORT S_AXIS_TREADY = TREADY, DIR=O, BUS=S_AXIS
PORT S_AXIS_TDATA = TDATA, DIR=I, VEC=[31:0], BUS=S_AXIS
PORT S_AXIS_TLAST = TLAST, DIR=I, BUS=S_AXIS
PORT S_AXIS_TVALID = TVALID, DIR=I, BUS=S_AXIS
PORT S_AXIS_TKEEP = TKEEP , DIR=I, VEC=[3:0], BUS=S_AXIS
PORT S_AXIS_TUSER = TUSER , DIR=I, VEC=[3:0], BUS=S_AXIS
PORT S_AXIS_TID = TID, DIR=I,VEC=[4:0], BUS=S_AXIS
PORT S_AXIS_TDEST = TDEST , DIR=I, VEC=[4:0], BUS=S_AXIS
PORT M_AXIS_ARESETN = ARESETN, DIR=I, SIGIS = RST
PORT M_AXIS_TVALID = TVALID, DIR=O, BUS=M_AXIS
PORT M_AXIS_TDATA = TDATA, DIR=O, VEC=[31:0], BUS=M_AXIS
PORT M_AXIS_TLAST = TLAST, DIR=O, BUS=M_AXIS
PORT M_AXIS_TREADY = TREADY, DIR=I, BUS=M_AXIS
PORT M_AXIS_TKEEP = TKEEP, DIR=O, VEC=[3:0], BUS=M_AXIS
PORT M_AXIS_TUSER = TUSER, DIR=O, VEC=[3:0], BUS=M_AXIS
PORT M_AXIS_TID = TID, DIR=O, VEC=[4:0], BUS=M_AXIS
PORT M_AXIS_TDEST = TDEST , DIR=O, VEC=[4:0], BUS=M_AXIS
PORT Ctrl_AXIS_ARESETN = ARESETN, DIR=I, SIGIS = RST
PORT Ctrl_AXIS_TREADY = TREADY, DIR=O, BUS=Ctrl_AXIS
PORT Ctrl_AXIS_TDATA = TDATA, DIR=I, VEC=[31:0], BUS=Ctrl_AXIS
PORT Ctrl_AXIS_TLAST = TLAST, DIR=I, BUS=Ctrl_AXIS
PORT Ctrl_AXIS_TVALID = TVALID, DIR=I, BUS=Ctrl_AXIS
PORT Ctrl_AXIS_TKEEP = TKEEP , DIR=I, VEC=[3:0], BUS=Ctrl_AXIS
PORT Status_AXIS_ARESETN = ARESETN, DIR=I, SIGIS = RST
PORT Status_AXIS_TDATA = TDATA, DIR=O, VEC=[31:0], BUS=Status_AXIS
PORT Status_AXIS_TKEEP = TKEEP, DIR=O, VEC=[3:0], BUS=Status_AXIS
PORT Status_AXIS_TVALID = TVALID, DIR=O, BUS=Status_AXIS
PORT Status_AXIS_TREADY = TREADY, DIR=I, BUS=Status_AXIS
PORT Status_AXIS_TLAST = TLAST, DIR=O, BUS=Status_AXIS
END
这样在模板生成的.v文件里调用Xilinx的FFT 核，就可以了，某些端口有用，某些没有用了。这个得仔细的设置好了，2对AXI Stream接口，还是很蛋疼的。
就这样，完成第一步骤工作，也就是创建好了封装有FFT的外设。
然后，就是使用AXI DMA外设了。在XPS下添加一个AXI DMA Engine设备，它有如下的接口：
1.S_AXI_LITE 连接到系统的axi4-lite总线上面；
2.M_AXI_SG 连接到AXI4总线上，直接连接内存；
3.M_AXI_MM2S，连接到AXI 总线上，AXI 总线直接连接内存ddr，相当于直接操作内存，将MM转换为Stream，为FFT提供数据；
4.M_AXI_S2MM，连接到AXI总线上，直接连接内存ddr，将Stream转换为MM，将FFT转换的数据输出；
5.M_AXIS_MM2S，为FFT提供数据，与FFT的Slave AXI Stream接口相连；
6.S_AXIS_S2MM，将FFT转换的数据取出，与FFT的Master AXI Stream相连；
7.M_AXIS_MM2S_CNTRL，用于控制，与FFT的Slave AXI Stream Config配置接口相连；
8.S_AXIS_S2MM_STS，用于查询，与FFT的Master AXI Stream Status状态接口相连。
真心是！！！！哎，8个接口，对应着上百个端口。
配置完成后。系统就完工了。
最担心的就是，这么纠结的FFT在系统里能否编译通过的问题了。
事实的确是很蛋疼，FFT的外设消耗资源太多，以至于我系统内原本有的定时器、中断控制器、各种GPIO、SPI设备等全部删除了。下图是所有的原有的设备都在的情况下，的资源消耗。它是无法implement的。因为完全超过了xc6slx16csg324的资源数目，特别是Slice。
最后，系统中的很多东西删掉之后才能implement，但也是极其的惊险。而且还是依靠我，手动控制map的参数。查阅Xilinx的命令行工具手册Command Line Tools User Guide，其中详细讲解了PARTGen、NetGen、DRC、NGDBuild、MAP、Physical Design Rule Check、Place and Route (PAR)、TRACE、BitGen、PROMGen等命令行工具的参数配置，可以达到怎样的效果。
我们关心的资源优化使用，时序，面积优化还是性能优化等等。都可以通过手动添加命令控制参数达到。
修改XPS中implementation Options File， 即etc目录下的fast_runtime.opt文件。加粗的为添加进来的。
FLOWTYPE = FPGA;
###############################################################
## Filename: fast_runtime.opt
##
## Option File For Xilinx FPGA Implementation Flow for Fast
## Runtime.
##
## Version: 4.1.1
###############################################################
#
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p ; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-bm .bmm # Block RAM memory map file
; # User design - pick from xflow command line
-uc .ucf; # ucf constraints
.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
#
# Options for Mapper
#
# Type "map -h " for a detailed list of map command line options
#
Program map
-o _map.ncd; # Output Mapped ncd file
-w; # Overwrite output files.
-pr b; # Pack internal FF/latches into IOBs
#-fp .mfp; # Floorplan file
-global_opt area;
-lc area;
-mt 4;
-ol high;
-timing;
-detail;
.ngd; # Input NGD file
.pcf; # Physical constraints file
END Program map
#
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o _map.twr; # Output trace report file
-xml _map.twx; # Output XML version of the timing report
#-tsi _map.tsi; # Produce Timing Specification Interaction report
_map.ncd; # Input mapped ncd
.pcf; # Physical constraints file
END Program post_map_trce
#
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
_map.ncd; # Input mapped NCD file
.ncd; # Output placed and routed NCD
.pcf; # Input physical constraints file
END Program par
#
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o .twr; # Output trace report file
-xml .twx; # Output XML version of the timing report
#-tsi .tsi; # Produce Timing Specification Interaction report
.ncd; # Input placed and routed ncd
.pcf; # Physical constraints file
END Program post_par_trce
主要是在map过程中进行面积优化，以节约资源，当然对microblaze处理器的配置的里面，最好也把面积优化选项加上。
经过这么一番手动折腾，最终能够完整的编译通过，得到bitstream文件了。
资源消耗情况如下.
Design Summary:
Number of errors: 0
Number of warnings: 28
Slice Logic Utilization:
Number of Slice Registers: 6,374 out of 18,224 34%
Number used as Flip Flops: 6,369
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 5
Number of Slice LUTs: 5,868 out of 9,112 64%
Number used as logic: 4,560 out of 9,112 50%
Number using O6 output only: 2,786
Number using O5 output only: 264
Number using O5 and O6: 1,510
Number used as ROM: 0
Number used as Memory: 647 out of 2,176 29%
Number used as Dual Port RAM: 152
Number using O6 output only: 64
Number using O5 output only: 2
Number using O5 and O6: 86
Number used as Single Port RAM: 0
Number used as Shift Register: 495
Number using O6 output only: 253
Number using O5 output only: 8
Number using O5 and O6: 234
Number used exclusively as route-thrus: 661
Number with same-slice register load: 588
Number with same-slice carry load: 64
Number with other load: 9
Slice Logic Distribution:
Number of occupied Slices: 2,221 out of 2,278 97%
Number of MUXCYs used: 1,024 out of 4,556 22%
Number of LUT Flip Flop pairs used: 6,836
Number with an unused Flip Flop: 1,769 out of 6,836 25%
Number with an unused LUT: 968 out of 6,836 14%
Number of fully used LUT-FF pairs: 4,099 out of 6,836 59%
Number of unique control sets: 417
Number of slice register sites lost
to control set restrictions: 1,696 out of 18,224 9%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 48 out of 232 20%
Number of LOCed IOBs: 48 out of 48 100%
IOB Flip Flops: 7
Specific Feature Utilization:
Number of RAMB16BWERs: 23 out of 32 71%
Number of RAMB8BWERs: 5 out of 64 7%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 2 out of 248 1%
Number used as ILOGIC2s: 2
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 23 out of 248 9%
Number used as IODELAY2s: 0
Number used as IODRP2s: 1
Number used as IODRP2_MCBs: 22
Number of OLOGIC2/OSERDES2s: 46 out of 248 18%
Number used as OLOGIC2s: 3
Number used as OSERDES2s: 43
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 1 out of 4 25%
Number of DSP48A1s: 8 out of 32 25%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 1 out of 2 50%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 2 50%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 747 MB
Total REAL time to MAP completion: 2 mins 51 secs
Total CPU time to MAP completion (all processors): 2 mins 56 secs
Mapping completed.
See MAP report file "system_map.mrp" for details.
#----------------------------------------------#
# Starting program par
# par -w -ol high system_map.ncd system.ncd system.pcf
#----------------------------------------------#
可以看到Slice用到极限了，真的是！！！
当再添加一个中断控制器后，编译。就更加有意思了，这个Slice消耗量竟然变少了~~~~
Design Summary
--------------
Number of errors: 0
Number of warnings: 28
Slice Logic Utilization:
Number of Slice Registers: 6,442 out of 18,224 35%
Number used as Flip Flops: 6,436
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 6
Number of Slice LUTs: 6,039 out of 9,112 66%
Number used as logic: 4,616 out of 9,112 50%
Number using O6 output only: 2,748
Number using O5 output only: 253
Number using O5 and O6: 1,615
Number used as ROM: 0
Number used as Memory: 647 out of 2,176 29%
Number used as Dual Port RAM: 152
Number using O6 output only: 64
Number using O5 output only: 2
Number using O5 and O6: 86
Number used as Single Port RAM: 0
Number used as Shift Register: 495
Number using O6 output only: 248
Number using O5 output only: 12
Number using O5 and O6: 235
Number used exclusively as route-thrus: 776
Number with same-slice register load: 699
Number with same-slice carry load: 63
Number with other load: 14
Slice Logic Distribution:
Number of occupied Slices: 2,207 out of 2,278 96%
Number of MUXCYs used: 1,028 out of 4,556 22%
Number of LUT Flip Flop pairs used: 6,791
Number with an unused Flip Flop: 1,785 out of 6,791 26%
Number with an unused LUT: 752 out of 6,791 11%
Number of fully used LUT-FF pairs: 4,254 out of 6,791 62%
Number of unique control sets: 427
Number of slice register sites lost
to control set restrictions: 1,748 out of 18,224 9%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 48 out of 232 20%
Number of LOCed IOBs: 48 out of 48 100%
IOB Flip Flops: 7
Specific Feature Utilization:
Number of RAMB16BWERs: 23 out of 32 71%
Number of RAMB8BWERs: 5 out of 64 7%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 2 out of 248 1%
Number used as ILOGIC2s: 2
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 23 out of 248 9%
Number used as IODELAY2s: 0
Number used as IODRP2s: 1
Number used as IODRP2_MCBs: 22
Number of OLOGIC2/OSERDES2s: 46 out of 248 18%
Number used as OLOGIC2s: 3
Number used as OSERDES2s: 43
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 1 out of 4 25%
Number of DSP48A1s: 8 out of 32 25%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 1 out of 2 50%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 2 50%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.56
Peak Memory Usage: 767 MB
既然这样，得寸咱就进个尺。再加一个定时器。
啊哈，也通过了，这回98%了。
Design Summary
--------------
Number of errors: 0
Number of warnings: 29
Slice Logic Utilization:
Number of Slice Registers: 6,664 out of 18,224 36%
Number used as Flip Flops: 6,658
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 6
Number of Slice LUTs: 6,242 out of 9,112 68%
Number used as logic: 4,937 out of 9,112 54%
Number using O6 output only: 3,053
Number using O5 output only: 277
Number using O5 and O6: 1,607
Number used as ROM: 0
Number used as Memory: 648 out of 2,176 29%
Number used as Dual Port RAM: 152
Number using O6 output only: 64
Number using O5 output only: 2
Number using O5 and O6: 86
Number used as Single Port RAM: 0
Number used as Shift Register: 496
Number using O6 output only: 248
Number using O5 output only: 14
Number using O5 and O6: 234
Number used exclusively as route-thrus: 657
Number with same-slice register load: 584
Number with same-slice carry load: 64
Number with other load: 9
Slice Logic Distribution:
Number of occupied Slices: 2,239 out of 2,278 98%
Number of MUXCYs used: 1,232 out of 4,556 27%
Number of LUT Flip Flop pairs used: 7,301
Number with an unused Flip Flop: 1,912 out of 7,301 26%
Number with an unused LUT: 1,059 out of 7,301 14%
Number of fully used LUT-FF pairs: 4,330 out of 7,301 59%
Number of unique control sets: 440
Number of slice register sites lost
to control set restrictions: 1,798 out of 18,224 9%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 48 out of 232 20%
Number of LOCed IOBs: 48 out of 48 100%
IOB Flip Flops: 7
Specific Feature Utilization:
Number of RAMB16BWERs: 23 out of 32 71%
Number of RAMB8BWERs: 5 out of 64 7%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 2 out of 248 1%
Number used as ILOGIC2s: 2
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 23 out of 248 9%
Number used as IODELAY2s: 0
Number used as IODRP2s: 1
Number used as IODRP2_MCBs: 22
Number of OLOGIC2/OSERDES2s: 46 out of 248 18%
Number used as OLOGIC2s: 3
Number used as OSERDES2s: 43
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 1 out of 4 25%
Number of DSP48A1s: 8 out of 32 25%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 1 out of 2 50%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 2 50%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.68
Peak Memory Usage: 774 MB
其实，FPGA开发过程中，implement过程真的是有看人品的，比较复杂的工程，可能某一次编译能过，而下一次又不能过。
因为这里面的布线，有一定的随机性。虽然用户可以对某些东西进行约束。但是工程复杂了，就难于控制了。只能反复编译，期待某一次的成功。
恩，人要知足，先这样吧，XPS下的工程内容就这么多了。
还得敲SDK下的代码，实现FFT变换呢。
啊，还是忍不住。加了一个串口uart lite，便于打印调试啊。。。
人品还可以，又编译过了。
Design Summary
--------------
Number of errors: 0
Number of warnings: 29
Slice Logic Utilization:
Number of Slice Registers: 6,753 out of 18,224 37%
Number used as Flip Flops: 6,747
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 6
Number of Slice LUTs: 6,412 out of 9,112 70%
Number used as logic: 5,009 out of 9,112 54%
Number using O6 output only: 3,067
Number using O5 output only: 293
Number using O5 and O6: 1,649
Number used as ROM: 0
Number used as Memory: 658 out of 2,176 30%
Number used as Dual Port RAM: 152
Number using O6 output only: 64
Number using O5 output only: 2
Number using O5 and O6: 86
Number used as Single Port RAM: 0
Number used as Shift Register: 506
Number using O6 output only: 248
Number using O5 output only: 16
Number using O5 and O6: 242
Number used exclusively as route-thrus: 745
Number with same-slice register load: 671
Number with same-slice carry load: 64
Number with other load: 10
Slice Logic Distribution:
Number of occupied Slices: 2,272 out of 2,278 99%
Number of MUXCYs used: 1,264 out of 4,556 27%
Number of LUT Flip Flop pairs used: 7,310
Number with an unused Flip Flop: 1,947 out of 7,310 26%
Number with an unused LUT: 898 out of 7,310 12%
Number of fully used LUT-FF pairs: 4,465 out of 7,310 61%
Number of unique control sets: 451
Number of slice register sites lost
to control set restrictions: 1,819 out of 18,224 9%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 50 out of 232 21%
Number of LOCed IOBs: 50 out of 50 100%
IOB Flip Flops: 9
Specific Feature Utilization:
Number of RAMB16BWERs: 23 out of 32 71%
Number of RAMB8BWERs: 5 out of 64 7%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 3 out of 248 1%
Number used as ILOGIC2s: 3
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 23 out of 248 9%
Number used as IODELAY2s: 0
Number used as IODRP2s: 1
Number used as IODRP2_MCBs: 22
Number of OLOGIC2/OSERDES2s: 47 out of 248 18%
Number used as OLOGIC2s: 4
Number used as OSERDES2s: 43
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 1 out of 4 25%
Number of DSP48A1s: 8 out of 32 25%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 1 out of 2 50%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 2 50%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.66
Peak Memory Usage: 783 MB
刚刚又翻看了FFT的文档，在它的performance and resource Usage中发现了map参数的的配置建议。原来如此！！！
bwb@STI 2014.08.19
转载：http://blog.sina.com.cn/s/blog_98740ded0102uzm6.html