http://en.wikipedia.org/wiki/SGPIO
SGPIO
The SGPIO specification is maintained by the Small Form Factor committee in the SFF-8485 standard. The International Blinking Pattern Interpretation indicates how SGPIO signals are interpreted into blinking light-emitting diodes (LEDs) on disk arrays and storage backplanes.
Contents
[hide]- 1 Host bus adapters
- 2 Backplanes with SGPIO bus interface
- 3 SGPIO interpretation and LED blinking patterns
- 4 Electrical characteristics of the SGPIO bus
- 5 Signal lines of the SGPIO bus
- 6 SGPIO implementation
- 7 Adoption of the SGPIO specification
- 8 SGPIO Timeout Conditions
- 9 Backplane Implementations of the SGPIO bus
- 10 External links
Host bus adapters[edit]
The SGPIO signal consists of 4 electrical signals; it typically originates from a host bus adapter (HBA). iPass connectors carry both SAS/SATA electrical connections between the HBA and the hard drives as well as the 4 SGPIO signals.
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Backplanes with SGPIO bus interface[edit]
A backplane is a circuit board with connectors and power circuitry into which hard drives are attached; they can have multiple slots, each of which can be populated with a hard drive. Typically the backplane is equipped with LEDs which by their colour and activity, indicate the slot's status; typically, a slot's LED will emit a particular colour or blink pattern to indicate its current status.
SGPIO interpretation and LED blinking patterns[edit]
Although many hardware vendors define their own proprietary LED blinking pattern, the common standard for SGPIO interpretation and LED blinking pattern can be found in the IBPI specification.
On backplanes, vendors use typically 2 or 3 LEDs per slot - in both implementations a green LED indicates presence and/or activity - for backplanes with 2 LEDs per slot, the second LED indicates Status whereas in backplanes with 3 LEDs the second and third indicate Locate and Fail.
Electrical characteristics of the SGPIO bus[edit]
The SGPIO bus consists of 4 signal lines and originates at the HBA, referred to as the initiator and ends at a backplane, referred to as the target. If a backplane (or target) is not present the HBA may still drive the bus without any harm to the system; if one does exist, it can communicate back to the HBA using the 4th wire.
The SGPIO bus is an open collector bus with 2.0 kΩ pull-up resistors located at the HBA and the backplane - as on any open collector bus information is transferred by devices on the bus pulling the lines to ground (GND) using an open collector transistor or open drain FET.
Signal lines of the SGPIO bus[edit]
SClock[edit]
The SGPIO bus has a dedicated clock line driven by the initiator (its maximum clock rate is 100 kHz), although many implementations use slower ones (typically 48 kHz).
SLoad[edit]
This line is synchronous to the clock and is used to indicate the start of a new frame of data; a new SGPIO frame is indicated by SLoad being high at a rising edge of a clock after having been low for at least 5 clock cycles. The following 4 falling clock edges after a start condition is used to carry a 4-bit value from the HBA to the backplane; the definition of this value is proprietary and varies between system vendors.
SDataOut[edit]
This line carries 3 bits of data from the HBA to the backplane: the first bit typically carries activity; the second bit carries locate; and the third bit carries fail. A low value for the first bit indicates no activity and a high value indicates activity.
SDataIn[edit]
This line is used by the backplane and indicates some condition on the backplane back to the HBA. The first bit being high commonly indicates the presence of a drive. The two following bits are typically unused, and driven low. Because this line would be high for all 3 bits when no backplane is connected, an HBA can detect the presence of a backplane by the second or third bit of the SDataIn being driven low.
The SDataIn and SdataOut then repeats with 3 clocks per drive until the last drive is reached, and the cycle starts over again.
SGPIO implementation[edit]
There are varieties in how the SGPIO bus is implemented between vendors of HBAs and storage controllers - some vendors will send a continuous stream of data which is advantageous to quickly update the LEDs on a backplane after a cables are removed and re-inserted, while others send data only when there is a need to update the LED pattern.
Adoption of the SGPIO specification[edit]
SGPIO and the SGPIO spec. is generally adopted and implemented in products from most major HBA and storage controller vendors such as LSI, Intel, Adaptec,Nvidia, Broadcom, Marvell Technology Group and PMC-Sierra. Most products shipping with support for SAS and SATA drives support this standard.
SGPIO Timeout Conditions[edit]
The SGPIO spec calls for the target to turn off all indicators when SClock, SLoad and SDataOut have been high for 64 ms; in practice this is not consistently followed by all vendors. Also, in some vendor's implementations the clock may be halted sporadically or stopped during or between cycles. Another, rather impractical, variation between vendors the state in which the clock is left after a cycle.
Backplane Implementations of the SGPIO bus[edit]
The idea behind this specification was to be able to use low cost CPLDs or microcontrollers on a backplane to drive LEDs; in practice, it has been found that there are variations in timing and interpretations of the bits between vendors, thus a simple CPLD would only work for a specific implementation thoroughly tested with one product from one vendor.[citation needed] A microcontroller is more applicable for this purpose, although the 4-bit SGPIO interface custom bus is not implemented on them[citation needed] - sampling of the 4-bit lines using GPIOs 100 kHz bit operations is too slow for many low-cost microcontrollers to handle whilst handling LED and other functions simultaneously. The length of the bit stream varies between HBA or storage controller; some vendors will stop the bit-stream when reaching the desired drive, while others will clock it all the way through. Some SAS-expander's bit streams may be as long as 108 (36×3) bits.
The safest implementation which ensures compatibility between all HBA and storage controller vendors is to use an ASIC, specifically, a combination of a microcontroller core with a hardware SGPIO interface; this concept was patented[citation needed] in 2006 by AMI and implemented in a series of backplane controller chips named the MG9071, MG9072, MG9077, and MG9082.
These chips will receive 1 or 2 SGPIO streams and drive LEDs accordingly; the latest chip from AMI, the MG9077, can be configured by pull-up and pull-down resistors to adopt to 16 different configurations of SGPIO buses and drive the LEDs accordingly. Since the availability of these chips from AMI, major OEMsincluding NEC, Hitachi, Supermicro, IBM, Sun Microsystems, and others are using them on their backplanes to receive the SGPIO streams from a variety of HBA vendors and on-board controller chips to consistently drive LEDs with a pre-determined blinking pattern.
External links[edit]
- SFF-8485 SGPIO specification
- SFF Documents (Documents & Specifications)
- Backplane Controllers from AMI