偶数分频
1 ibrary IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 use ieee.std_logic_arith; 4 use ieee.std_logic_unsigned; 5 6 7 entity test_1 is 8 generic (n: integer:=6); 9 port( 10 clkin: in std_logic;-----rate=n,n is odd; 11 clkout: out std_logic ---relative FPGA,clkout is out signal; 12 ); 13 end test_1; 14 15 architecture Behavioral of test_1 is 16 signal cnt:integer range 0 to n-1; 17 begin 18 process (clkin)------count 19 begin 20 if (clkin'event and clkin='1') then 21 if(cnt<n-1) then 22 cnt<=cnt+1; 23 else 24 cnt<=0; 25 end if; 26 end if; 27 end process; 28 29 process(cnt) -----根据计数值，控制输出始终脉冲的高低电平 30 begin 31 if(cnt<n/2) then 32 clkout<='1'; 33 else 34 clkout<='0'; 35 end if; 36 end process; 37 38 39 end Behavioral;
1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 use ieee.std_logic_arith; 4 use ieee.std_logic_unsigned; 5 6 7 -- Uncomment the following library declaration if using 8 -- arithmetic functions with Signed or Unsigned values 9 --use IEEE.NUMERIC_STD.ALL; 10 11 -- Uncomment the following library declaration if instantiating 12 -- any Xilinx primitives in this code. 13 --library UNISIM; 14 --use UNISIM.VComponents.all; 15 16 entity test_1 is 17 generic (n: integer:=10); 18 port( 19 clkin: in std_logic;-----rate=n,n is odd; 20 clkout: out std_logic ---relative FPGA,clkout is out signal; 21 ); 22 end test_1; 23 24 architecture Behavioral of test_1 is 25 signal cnt:integer range 0 to n/2-1; 26 signal temp :std_logic; 27 begin 28 process (clkin)------count 29 begin 30 if (clkin'event and clkin='1') then 31 if(cnt=n/2-1) then 32 cnt<=0; 33 temp<=not temp; 34 else 35 cnt<=cnt+1; 36 end if; 37 end if; 38 end process; 39 40 41 clkout<=temp;---clkout和temp都是信号，均可传出来 42 43 44 end Behavioral;
奇偶分频
1 entity test_1 is 2 generic (n: integer:=5); 3 port( 4 clkin: in std_logic;-----rate=n,n is 偶数; 5 clkout: out std_logic ---relative FPGA,clkout is out signal; 6 ); 7 end test_1; 8 9 architecture Behavioral of test_1 is 10 signal cnt1,cnt2:integer range 0 to n/2-1; 11 12 begin 13 process (clkin)------count 14 begin 15 if (clkin'event and clkin='1') then ------上升沿计数 16 if(cnt1<n-1) then 17 cnt1<=cnt1+1; 18 19 else 20 cnt1<=0; 21 end if; 22 end if; 23 end process; 24 25 process (clkin)------count 26 begin 27 if (clkin'event and clkin='0') then ------下升沿计数 28 if(cnt2<n-1) then 29 cnt2<=cnt2+1; 30 31 else 32 cnt2<=0; 33 end if; 34 end if; 35 end process; 36 37 38 clkout<='1' when cnt1<(n-1)/2 else 39 '0' when cnt2<(n-1)/2; 40 41 42 end Behavioral;
占空标准
1 entity test_1 is----占空比3：:1 的偶数分频器 2 -----当计数值为0-2时，输出高电平，到计数值为 3 ---3-9时，输出低电平 4 generic ( 5 n: integer:=10; 6 m: integer:=3 ----占空比为m:n,rate=n; 7 ); 8 port( 9 clkin: in std_logic;-----rate=n,n is 偶数; 10 clkout: out std_logic ---relative FPGA,clkout is out signal; 11 ); 12 end test_1; 13 14 architecture Behavioral of test_1 is 15 signal cnt1:integer range 0 to n-1; 16 17 begin 18 process (clkin)------count 19 begin 20 if (clkin'event and clkin='1') then ------上升沿计数 21 if(cnt1<n-1) then 22 cnt1<=cnt1+1; 23 24 else 25 cnt1<=0; 26 end if; 27 end if; 28 end process; 29 30 31 32 clkout<='1' when cnt1<m else 33 '0' ; 34 35 36 end Behavioral;